<p>Patrick Rudolph has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20907">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/sandybridge/raminit: Add Kconfig option for fuses<br><br>Add a new Kconfig option to ignore memory fuses that limit the<br>maximum DRAM frequency to be used. The option is disabled by<br>default and should only enabled by experienced users as it<br>might decrease system stability or prevent a successful RAM<br>training.<br><br>Remove conflicting devicetree settings.<br><br>Change-Id: I35dd78a02bcaafce8ba522d253c795d7835bacae<br>Signed-off-by: Patrick Rudolph <siro@das-labor.org><br>---<br>M src/mainboard/lenovo/l520/devicetree.cb<br>M src/mainboard/lenovo/t420/devicetree.cb<br>M src/mainboard/lenovo/t420s/devicetree.cb<br>M src/mainboard/lenovo/t430/devicetree.cb<br>M src/mainboard/lenovo/t430s/devicetree.cb<br>M src/mainboard/lenovo/t520/devicetree.cb<br>M src/mainboard/lenovo/t530/devicetree.cb<br>M src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb<br>M src/mainboard/lenovo/x220/devicetree.cb<br>M src/mainboard/lenovo/x230/devicetree.cb<br>M src/northbridge/intel/sandybridge/Kconfig<br>M src/northbridge/intel/sandybridge/raminit_common.c<br>12 files changed, 15 insertions(+), 30 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/20907/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb<br>index 542b06a..3e1f308 100644<br>--- a/src/mainboard/lenovo/l520/devicetree.cb<br>+++ b/src/mainboard/lenovo/l520/devicetree.cb<br>@@ -15,9 +15,6 @@<br> register "gpu_panel_power_up_delay" = "0"<br> register "gpu_pch_backlight" = "0x00000000"<br> <br>- # Override fuse bits that hard-code the value to 666 Mhz<br>- register "max_mem_clock_mhz" = "933"<br>-<br> device cpu_cluster 0x0 on<br> chip cpu/intel/socket_rPGA989<br> device lapic 0x0 on<br>diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb<br>index deb62b7..4c90a5e 100644<br>--- a/src/mainboard/lenovo/t420/devicetree.cb<br>+++ b/src/mainboard/lenovo/t420/devicetree.cb<br>@@ -18,9 +18,6 @@<br> register "gpu_cpu_backlight" = "0x1155"<br> register "gpu_pch_backlight" = "0x06100610"<br> <br>- # Override fuse bits that hard-code the value to 666 Mhz<br>- register "max_mem_clock_mhz" = "933"<br>-<br> device cpu_cluster 0 on<br> chip cpu/intel/socket_rPGA988B<br> device lapic 0 on end<br>diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb<br>index 3224322..655d39c 100644<br>--- a/src/mainboard/lenovo/t420s/devicetree.cb<br>+++ b/src/mainboard/lenovo/t420s/devicetree.cb<br>@@ -17,9 +17,6 @@<br> register "gpu_cpu_backlight" = "0x1155"<br> register "gpu_pch_backlight" = "0x06100610"<br> <br>- # Override fuse bits that hard-code the value to 666 Mhz<br>- register "max_mem_clock_mhz" = "933"<br>-<br> device cpu_cluster 0 on<br> chip cpu/intel/socket_rPGA988B<br> device lapic 0 on end<br>diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb<br>index 0a121b7..cc2d43f 100644<br>--- a/src/mainboard/lenovo/t430/devicetree.cb<br>+++ b/src/mainboard/lenovo/t430/devicetree.cb<br>@@ -34,9 +34,6 @@<br> end<br> end<br> <br>- # Override fuse bits that hard-code the value to 666 Mhz<br>- register "max_mem_clock_mhz" = "933"<br>-<br> device domain 0x0 on<br> chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH<br> register "c2_latency" = "0x0065"<br>diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb<br>index ccee86a..6846879 100644<br>--- a/src/mainboard/lenovo/t430s/devicetree.cb<br>+++ b/src/mainboard/lenovo/t430s/devicetree.cb<br>@@ -17,9 +17,6 @@<br> register "gpu_cpu_backlight" = "0x1155"<br> register "gpu_pch_backlight" = "0x11551155"<br> <br>- # Override fuse bits that hard-code the value to 666 Mhz<br>- register "max_mem_clock_mhz" = "933"<br>-<br> device cpu_cluster 0 on<br> chip cpu/intel/socket_rPGA989<br> device lapic 0 on end<br>diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb<br>index 0065799..55f838a 100644<br>--- a/src/mainboard/lenovo/t520/devicetree.cb<br>+++ b/src/mainboard/lenovo/t520/devicetree.cb<br>@@ -18,9 +18,6 @@<br> register "gpu_cpu_backlight" = "0x1155"<br> register "gpu_pch_backlight" = "0x06100610"<br> <br>- # Override fuse bits that hard-code the value to 666 Mhz<br>- register "max_mem_clock_mhz" = "933"<br>-<br> device cpu_cluster 0 on<br> chip cpu/intel/socket_rPGA988B<br> device lapic 0 on end<br>diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb<br>index 2047a78..9f494b9 100644<br>--- a/src/mainboard/lenovo/t530/devicetree.cb<br>+++ b/src/mainboard/lenovo/t530/devicetree.cb<br>@@ -18,9 +18,6 @@<br> register "gpu_cpu_backlight" = "0x1155"<br> register "gpu_pch_backlight" = "0x11551155"<br> <br>- # Override fuse bits that hard-code the value to 666 Mhz<br>- register "max_mem_clock_mhz" = "933"<br>-<br> device cpu_cluster 0 on<br> chip cpu/intel/socket_rPGA989<br> device lapic 0 on end<br>diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb<br>index ce74d3f..e76f68a 100644<br>--- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb<br>+++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb<br>@@ -15,9 +15,6 @@<br> register "gpu_panel_power_up_delay" = "300"<br> register "gpu_pch_backlight" = "0x11551155"<br> <br>- # Override fuse bits that hard-code the value to 666 Mhz<br>- register "max_mem_clock_mhz" = "933"<br>-<br> device cpu_cluster 0 on<br> chip cpu/intel/socket_rPGA989<br> device lapic 0 on end<br>diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb<br>index 62ad3b0..2bac65d 100644<br>--- a/src/mainboard/lenovo/x220/devicetree.cb<br>+++ b/src/mainboard/lenovo/x220/devicetree.cb<br>@@ -18,9 +18,6 @@<br> register "gpu_cpu_backlight" = "0x1155"<br> register "gpu_pch_backlight" = "0x06100610"<br> <br>- # Override fuse bits that hard-code the value to 666 Mhz<br>- register "max_mem_clock_mhz" = "933"<br>-<br> device cpu_cluster 0 on<br> chip cpu/intel/socket_rPGA989<br> device lapic 0 on end<br>diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb<br>index a1b0662..7a96a77 100644<br>--- a/src/mainboard/lenovo/x230/devicetree.cb<br>+++ b/src/mainboard/lenovo/x230/devicetree.cb<br>@@ -18,9 +18,6 @@<br> register "gpu_cpu_backlight" = "0x1155"<br> register "gpu_pch_backlight" = "0x11551155"<br> <br>- # Override fuse bits that hard-code the value to 666 Mhz<br>- register "max_mem_clock_mhz" = "933"<br>-<br> device cpu_cluster 0 on<br> chip cpu/intel/socket_rPGA989<br> device lapic 0 on end<br>diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig<br>index ae5ddfc..5a7ec46 100644<br>--- a/src/northbridge/intel/sandybridge/Kconfig<br>+++ b/src/northbridge/intel/sandybridge/Kconfig<br>@@ -44,6 +44,18 @@<br> Select if you want to use coreboot implementation of raminit rather than<br> System Agent/MRC.bin. You should answer Y.<br> <br>+config NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES<br>+ bool "Ignore vendor programmed fuses that limit max. DRAM frequency"<br>+ default n<br>+ depends on USE_NATIVE_RAMINIT<br>+ help<br>+ Ignore the mainboard's vendor programmed fuses that might limit the<br>+ maximum DRAM frequency. By selecting this option the fuses will be<br>+ ignored and the only limits on DRAM frequency are set by RAM's SPD and<br>+ hard fuses in southbridge's clockgen.<br>+ Disabled by default as it might causes system instability.<br>+ Handle with care!<br>+<br> config CBFS_SIZE<br> hex<br> default 0x100000<br>diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c<br>index c6ff551..3e69f4d 100644<br>--- a/src/northbridge/intel/sandybridge/raminit_common.c<br>+++ b/src/northbridge/intel/sandybridge/raminit_common.c<br>@@ -402,6 +402,9 @@<br> <br> /* If this is zero, it just means devicetree.cb didn't set it */<br> if (!cfg || cfg->max_mem_clock_mhz == 0) {<br>+ if (IS_ENABLED(CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES))<br>+ return TCK_1333MHZ;<br>+<br> rev = pci_read_config8(PCI_DEV(0, 0, 0), PCI_DEVICE_ID);<br> <br> if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {<br></pre><p>To view, visit <a href="https://review.coreboot.org/20907">change 20907</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20907"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I35dd78a02bcaafce8ba522d253c795d7835bacae </div>
<div style="display:none"> Gerrit-Change-Number: 20907 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Patrick Rudolph <siro@das-labor.org> </div>