[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Enable UART debug port in bootblock always

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/20835


Change subject: soc/intel/skylake: Enable UART debug port in bootblock always
......................................................................

soc/intel/skylake: Enable UART debug port in bootblock always

Irrespective of whether UART_DEBUG is enabled in coreboot or not,
always enable UART controller for the debug port. This is required
because: UART hardware loses power while the system is
suspended. Linux kernel does not re-initialize the UART controller on
resume and so when serial console is enabled in kernel, it can result
in hangs on resume from S3. On platforms like baytrail, this was
handled in a similar way by initializing UART controller on
resume(https://chromium-review.googlesource.com/188011). In this
change, UART is always initialized in bootblock irrespective of normal
or S3 resume flow in order to re-use the UART drivers that are already
implemented and avoid redundancy.

BUG=b:64030366
TEST=Verified that kernel does not hang with the following sequence:
echo 'N' > /sys/module/printk/parameters/console_suspend
echo mem > /sys/power/state
<Resume from S3>

Change-Id: Ic936ac2a787fdc83935103c3ce4ed8f124a97a89
---
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/Makefile.inc
M src/soc/intel/skylake/bootblock/bootblock.c
M src/soc/intel/skylake/bootblock/uart.c
4 files changed, 7 insertions(+), 8 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/20835/1

diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 32c2654..dd4de53 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -84,6 +84,9 @@
 	select ACPI_NHLT
 	select HAVE_FSP_GOP
 	select SOC_INTEL_COMMON_GFX_OPREGION
+	select DRIVERS_UART
+	select DRIVERS_UART_8250MEM_32
+	select NO_UART_ON_SUPERIO
 
 config MAINBOARD_USES_FSP2_0
 	bool
@@ -196,9 +199,6 @@
 	bool "Enable UART debug port."
 	default n
 	select CONSOLE_SERIAL
-	select DRIVERS_UART
-	select DRIVERS_UART_8250MEM_32
-	select NO_UART_ON_SUPERIO
 
 config SKYLAKE_SOC_PCH_H
 	bool
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 7f618d4..7b8e149 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -14,8 +14,8 @@
 bootblock-y += i2c.c
 bootblock-y += bootblock/pch.c
 bootblock-y += bootblock/report_platform.c
-bootblock-$(CONFIG_UART_DEBUG) += bootblock/uart.c
-bootblock-$(CONFIG_UART_DEBUG) += uart_debug.c
+bootblock-y += bootblock/uart.c
+bootblock-y += uart_debug.c
 bootblock-y += gpio.c
 bootblock-y += gspi.c
 bootblock-y += pch.c
diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c
index 058cec8..ac87f41 100644
--- a/src/soc/intel/skylake/bootblock/bootblock.c
+++ b/src/soc/intel/skylake/bootblock/bootblock.c
@@ -30,9 +30,7 @@
 	bootblock_pch_early_init();
 	bootblock_cpu_init();
 	pch_early_iorange_init();
-
-	if (IS_ENABLED(CONFIG_UART_DEBUG))
-		pch_uart_init();
+	pch_uart_init();
 }
 
 void bootblock_soc_init(void)
diff --git a/src/soc/intel/skylake/bootblock/uart.c b/src/soc/intel/skylake/bootblock/uart.c
index 26b81c0..eedf75c 100644
--- a/src/soc/intel/skylake/bootblock/uart.c
+++ b/src/soc/intel/skylake/bootblock/uart.c
@@ -53,4 +53,5 @@
 			PCR_SIO_PCH_LEGACY_UART2);
 
 	gpio_configure_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+	uart_init(CONFIG_UART_FOR_CONSOLE);
 }

-- 
To view, visit https://review.coreboot.org/20835
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ic936ac2a787fdc83935103c3ce4ed8f124a97a89
Gerrit-Change-Number: 20835
Gerrit-PatchSet: 1
Gerrit-Owner: Furquan Shaikh <furquan at google.com>
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