<p>Furquan Shaikh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20835">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Enable UART debug port in bootblock always<br><br>Irrespective of whether UART_DEBUG is enabled in coreboot or not,<br>always enable UART controller for the debug port. This is required<br>because: UART hardware loses power while the system is<br>suspended. Linux kernel does not re-initialize the UART controller on<br>resume and so when serial console is enabled in kernel, it can result<br>in hangs on resume from S3. On platforms like baytrail, this was<br>handled in a similar way by initializing UART controller on<br>resume(https://chromium-review.googlesource.com/188011). In this<br>change, UART is always initialized in bootblock irrespective of normal<br>or S3 resume flow in order to re-use the UART drivers that are already<br>implemented and avoid redundancy.<br><br>BUG=b:64030366<br>TEST=Verified that kernel does not hang with the following sequence:<br>echo 'N' > /sys/module/printk/parameters/console_suspend<br>echo mem > /sys/power/state<br><Resume from S3><br><br>Change-Id: Ic936ac2a787fdc83935103c3ce4ed8f124a97a89<br>---<br>M src/soc/intel/skylake/Kconfig<br>M src/soc/intel/skylake/Makefile.inc<br>M src/soc/intel/skylake/bootblock/bootblock.c<br>M src/soc/intel/skylake/bootblock/uart.c<br>4 files changed, 7 insertions(+), 8 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/20835/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig<br>index 32c2654..dd4de53 100644<br>--- a/src/soc/intel/skylake/Kconfig<br>+++ b/src/soc/intel/skylake/Kconfig<br>@@ -84,6 +84,9 @@<br> select ACPI_NHLT<br> select HAVE_FSP_GOP<br> select SOC_INTEL_COMMON_GFX_OPREGION<br>+ select DRIVERS_UART<br>+ select DRIVERS_UART_8250MEM_32<br>+ select NO_UART_ON_SUPERIO<br> <br> config MAINBOARD_USES_FSP2_0<br> bool<br>@@ -196,9 +199,6 @@<br> bool "Enable UART debug port."<br> default n<br> select CONSOLE_SERIAL<br>- select DRIVERS_UART<br>- select DRIVERS_UART_8250MEM_32<br>- select NO_UART_ON_SUPERIO<br> <br> config SKYLAKE_SOC_PCH_H<br> bool<br>diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc<br>index 7f618d4..7b8e149 100644<br>--- a/src/soc/intel/skylake/Makefile.inc<br>+++ b/src/soc/intel/skylake/Makefile.inc<br>@@ -14,8 +14,8 @@<br> bootblock-y += i2c.c<br> bootblock-y += bootblock/pch.c<br> bootblock-y += bootblock/report_platform.c<br>-bootblock-$(CONFIG_UART_DEBUG) += bootblock/uart.c<br>-bootblock-$(CONFIG_UART_DEBUG) += uart_debug.c<br>+bootblock-y += bootblock/uart.c<br>+bootblock-y += uart_debug.c<br> bootblock-y += gpio.c<br> bootblock-y += gspi.c<br> bootblock-y += pch.c<br>diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c<br>index 058cec8..ac87f41 100644<br>--- a/src/soc/intel/skylake/bootblock/bootblock.c<br>+++ b/src/soc/intel/skylake/bootblock/bootblock.c<br>@@ -30,9 +30,7 @@<br> bootblock_pch_early_init();<br> bootblock_cpu_init();<br> pch_early_iorange_init();<br>-<br>- if (IS_ENABLED(CONFIG_UART_DEBUG))<br>- pch_uart_init();<br>+ pch_uart_init();<br> }<br> <br> void bootblock_soc_init(void)<br>diff --git a/src/soc/intel/skylake/bootblock/uart.c b/src/soc/intel/skylake/bootblock/uart.c<br>index 26b81c0..eedf75c 100644<br>--- a/src/soc/intel/skylake/bootblock/uart.c<br>+++ b/src/soc/intel/skylake/bootblock/uart.c<br>@@ -53,4 +53,5 @@<br> PCR_SIO_PCH_LEGACY_UART2);<br> <br> gpio_configure_pads(uart2_pads, ARRAY_SIZE(uart2_pads));<br>+ uart_init(CONFIG_UART_FOR_CONSOLE);<br> }<br></pre><p>To view, visit <a href="https://review.coreboot.org/20835">change 20835</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20835"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic936ac2a787fdc83935103c3ce4ed8f124a97a89 </div>
<div style="display:none"> Gerrit-Change-Number: 20835 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Furquan Shaikh <furquan@google.com> </div>