[coreboot-gerrit] Change in coreboot[master]: [WIP]soc/intel/common/block: Add Intel PMC support
Shaunak Saha (Code Review)
gerrit at coreboot.org
Tue Apr 18 20:25:44 CEST 2017
Shaunak Saha has uploaded a new change for review. ( https://review.coreboot.org/19349 )
Change subject: [WIP]soc/intel/common/block: Add Intel PMC support
......................................................................
[WIP]soc/intel/common/block: Add Intel PMC support
Create common Intel PMC code.
Change-Id: Ic3d96fc23a98c30e8ea0969a7be09d217eeaa889
Signed-off-by: Shaunak Saha <shaunak.saha at intel.com>
---
A src/soc/intel/common/block/include/intelblocks/pmc.h
A src/soc/intel/common/block/pmc/Kconfig
A src/soc/intel/common/block/pmc/Makefile.inc
A src/soc/intel/common/block/pmc/pmc.c
4 files changed, 405 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/19349/1
diff --git a/src/soc/intel/common/block/include/intelblocks/pmc.h b/src/soc/intel/common/block/include/intelblocks/pmc.h
new file mode 100644
index 0000000..a354ce6
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/pmc.h
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_COMMON_PMC_H
+#define SOC_INTEL_COMMON_PMC_H
+
+/* SMI */
+uint32_t pmc_reset_smi_status(void);
+uint32_t pmc_clear_smi_status(void);
+uint32_t pmc_get_smi_en(void);
+void pmc_enable_smi(uint32_t mask);
+void pmc_disable_smi(uint32_t mask);
+
+/* PM1 */
+void pmc_enable_pm1_control(uint32_t mask);
+void pmc_disable_pm1_control(uint32_t mask);
+void pmc_enable_pm1(uint16_t events);
+uint16_t pmc_clear_pm1_status(void);
+
+/* TCO */
+uint32_t pmc_clear_tco_status(void);
+
+/* GPE */
+void pmc_enable_gpe(uint32_t mask);
+void pmc_disable_gpe(uint32_t mask);
+void pmc_disable_all_gpe(void);
+uint32_t pmc_clear_gpe_status(void);
+void clear_pmc_status(void);
+void pmc_clear_gpi_gpe_sts(void);
+
+void pmc_global_reset_enable(bool enable);
+void pmc_global_reset_lock(void);
+
+#endif /* SOC_INTEL_COMMON_SA_H */
+
diff --git a/src/soc/intel/common/block/pmc/Kconfig b/src/soc/intel/common/block/pmc/Kconfig
new file mode 100644
index 0000000..59d4075
--- /dev/null
+++ b/src/soc/intel/common/block/pmc/Kconfig
@@ -0,0 +1,4 @@
+config SOC_INTEL_COMMON_BLOCK_PMC
+ bool
+ help
+ Intel Processor common code for PMC
diff --git a/src/soc/intel/common/block/pmc/Makefile.inc b/src/soc/intel/common/block/pmc/Makefile.inc
new file mode 100644
index 0000000..4615192
--- /dev/null
+++ b/src/soc/intel/common/block/pmc/Makefile.inc
@@ -0,0 +1,4 @@
+bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c
+romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c
+smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c
diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c
new file mode 100644
index 0000000..e5ff8bd
--- /dev/null
+++ b/src/soc/intel/common/block/pmc/pmc.c
@@ -0,0 +1,350 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/pci_def.h>
+#include <halt.h>
+#include <intelblocks/pmc.h>
+#include <soc/gpe.h>
+#include <soc/iomap.h>
+#include <soc/pm.h>
+#include <soc/pci_devs.h>
+#include <timer.h>
+#include <vboot/vboot_common.h>
+
+static void print_num_status_bits(int num_bits, uint32_t status,
+ const char * const bit_names[])
+{
+ int i;
+
+ if (!status)
+ return;
+
+ for (i = num_bits - 1; i >= 0; i--) {
+ if (status & (1 << i)) {
+ if (bit_names[i])
+ printk(BIOS_DEBUG, "%s ", bit_names[i]);
+ else
+ printk(BIOS_DEBUG, "BIT%d ", i);
+ }
+ }
+}
+
+static uint32_t print_smi_status(uint32_t smi_sts)
+{
+ static const char * const smi_sts_bits[] = {
+ #define SMI_STS_DEF
+ #include <soc/bit_def.h>
+ };
+
+ if (!smi_sts)
+ return 0;
+
+ printk(BIOS_DEBUG, "SMI_STS: ");
+ print_num_status_bits(ARRAY_SIZE(smi_sts_bits), smi_sts, smi_sts_bits);
+ printk(BIOS_DEBUG, "\n");
+
+ return smi_sts;
+}
+
+uint32_t pmc_reset_smi_status(void)
+{
+ uint32_t smi_sts = inl(ACPI_PMIO_BASE + SMI_STS);
+ outl(smi_sts, ACPI_PMIO_BASE + SMI_STS);
+ return smi_sts;
+}
+
+uint32_t pmc_clear_smi_status(void)
+{
+ uint32_t sts = pmc_reset_smi_status();
+
+ /*
+ * Check for power button status if nothing else is indicating an SMI
+ * and SMIs aren't turned into SCIs. Apparently, there is no PM1 status
+ * bit in the SMI status register. That makes things difficult for
+ * determining if the power button caused an SMI.
+ */
+ if (sts == 0 && !(inl(ACPI_PMIO_BASE + PM1_CNT) & SCI_EN)) {
+ uint16_t pm1_sts = inw(ACPI_PMIO_BASE + PM1_STS);
+
+ /* Fake PM1 status bit if power button pressed. */
+ if (pm1_sts & PWRBTN_STS)
+ sts |= (1 << FAKE_PM1_SMI_STS);
+ }
+
+ return print_smi_status(sts);
+}
+
+uint32_t pmc_get_smi_en(void)
+{
+ return inl(ACPI_PMIO_BASE + SMI_EN);
+}
+
+void pmc_enable_smi(uint32_t mask)
+{
+ uint32_t smi_en = inl(ACPI_PMIO_BASE + SMI_EN);
+ smi_en |= mask;
+ outl(smi_en, ACPI_PMIO_BASE + SMI_EN);
+}
+
+void pmc_disable_smi(uint32_t mask)
+{
+ uint32_t smi_en = inl(ACPI_PMIO_BASE + SMI_EN);
+ smi_en &= ~mask;
+ outl(smi_en, ACPI_PMIO_BASE + SMI_EN);
+}
+
+/* PM1 */
+void pmc_enable_pm1(uint16_t events)
+{
+ outw(events, ACPI_PMIO_BASE + PM1_EN);
+}
+
+void pmc_enable_pm1_control(uint32_t mask)
+{
+ uint32_t pm1_cnt = inl(ACPI_PMIO_BASE + PM1_CNT);
+ pm1_cnt |= mask;
+ outl(pm1_cnt, ACPI_PMIO_BASE + PM1_CNT);
+}
+
+void pmc_disable_pm1_control(uint32_t mask)
+{
+ uint32_t pm1_cnt = inl(ACPI_PMIO_BASE + PM1_CNT);
+ pm1_cnt &= ~mask;
+ outl(pm1_cnt, ACPI_PMIO_BASE + PM1_CNT);
+}
+
+static uint16_t reset_pm1_status(void)
+{
+ uint16_t pm1_sts = inw(ACPI_PMIO_BASE + PM1_STS);
+ outw(pm1_sts, ACPI_PMIO_BASE + PM1_STS);
+ return pm1_sts;
+}
+
+static uint16_t print_pm1_status(uint16_t pm1_sts)
+{
+ static const char * const pm1_sts_bits[] = {
+ #define PM1_STS_DEF
+ #include <soc/bit_def.h>
+ };
+
+ if (!pm1_sts)
+ return 0;
+
+ printk(BIOS_SPEW, "PM1_STS: ");
+ print_num_status_bits(ARRAY_SIZE(pm1_sts_bits), pm1_sts, pm1_sts_bits);
+ printk(BIOS_SPEW, "\n");
+
+ return pm1_sts;
+}
+
+uint16_t pmc_clear_pm1_status(void)
+{
+ return print_pm1_status(reset_pm1_status());
+}
+
+/* TCO */
+static uint32_t print_tco_status(uint32_t tco_sts)
+{
+ static const char * const tco_sts_bits[] = {
+ #define TCO_STS_DEF
+ #include <soc/bit_def.h>
+ };
+
+ if (!tco_sts)
+ return 0;
+
+ printk(BIOS_DEBUG, "TCO_STS: ");
+ print_num_status_bits(ARRAY_SIZE(tco_sts_bits), tco_sts, tco_sts_bits);
+ printk(BIOS_DEBUG, "\n");
+
+ return tco_sts;
+}
+
+static uint32_t reset_tco_status(void)
+{
+ uint32_t tco_sts = inl(ACPI_PMIO_BASE + TCO_STS);
+ uint32_t tco_en = inl(ACPI_PMIO_BASE + TCO1_CNT);
+
+ outl(tco_sts, ACPI_PMIO_BASE + TCO_STS);
+ return tco_sts & tco_en;
+}
+
+uint32_t pmc_clear_tco_status(void)
+{
+ return print_tco_status(reset_tco_status());
+}
+
+/* GPE */
+void pmc_enable_gpe(uint32_t mask)
+{
+ uint32_t gpe0a_en = inl(ACPI_PMIO_BASE + GPE0_EN(0));
+ gpe0a_en |= mask;
+ outl(gpe0a_en, ACPI_PMIO_BASE + GPE0_EN(0));
+}
+
+void pmc_disable_gpe(uint32_t mask)
+{
+ uint32_t gpe0a_en = inl(ACPI_PMIO_BASE + GPE0_EN(0));
+ gpe0a_en &= ~mask;
+ outl(gpe0a_en, ACPI_PMIO_BASE + GPE0_EN(0));
+}
+
+void pmc_disable_all_gpe(void)
+{
+ pmc_disable_gpe(~0);
+}
+
+/* Clear the gpio gpe0 status bits in ACPI registers */
+void pmc_clear_gpi_gpe_sts(void)
+{
+ int i;
+
+ for (i = 1; i < GPE0_REG_MAX; i++) {
+ uint32_t gpe_sts = inl(ACPI_PMIO_BASE + GPE0_STS(i));
+ outl(gpe_sts, ACPI_PMIO_BASE + GPE0_STS(i));
+ }
+}
+
+static uint32_t reset_gpe_status(void)
+{
+ uint32_t gpe_sts = inl(ACPI_PMIO_BASE + GPE0_STS(0));
+ outl(gpe_sts, ACPI_PMIO_BASE + GPE0_STS(0));
+ return gpe_sts;
+}
+
+static uint32_t print_gpe_sts(uint32_t gpe_sts)
+{
+ static const char * const gpe_sts_bits[] = {
+ #define GPE_STS_DEF
+ #include <soc/bit_def.h>
+ };
+
+ if (!gpe_sts)
+ return gpe_sts;
+
+ printk(BIOS_DEBUG, "GPE0a_STS: ");
+ print_num_status_bits(ARRAY_SIZE(gpe_sts_bits), gpe_sts, gpe_sts_bits);
+ printk(BIOS_DEBUG, "\n");
+
+ return gpe_sts;
+}
+
+uint32_t pmc_clear_gpe_status(void)
+{
+ return print_gpe_sts(reset_gpe_status());
+}
+
+void clear_pmc_status(void)
+{
+ uint32_t prsts;
+ uint32_t gen_pmcon1;
+ uintptr_t pmc_bar0 = read_pmc_mmio_bar();
+
+ prsts = read32((void *)(pmc_bar0 + PRSTS));
+ gen_pmcon1 = read32((void *)(pmc_bar0 + GEN_PMCON1));
+
+ /* Clear the status bits. The RPS field is cleared on a 0 write. */
+ write32((void *)(pmc_bar0 + GEN_PMCON1), gen_pmcon1 & ~RPS);
+ write32((void *)(pmc_bar0 + PRSTS), prsts);
+}
+
+/* Read and clear GPE status (defined in arch/acpi.h) */
+int acpi_get_gpe(int gpe)
+{
+ int bank;
+ uint32_t mask, sts;
+ struct stopwatch sw;
+ int rc = 0;
+
+ if (gpe < 0 || gpe > GPE_MAX)
+ return -1;
+
+ bank = gpe / 32;
+ mask = 1 << (gpe % 32);
+
+ /* Wait up to 1ms for GPE status to clear */
+ stopwatch_init_msecs_expire(&sw, 1);
+ do {
+ if (stopwatch_expired(&sw))
+ return rc;
+
+ sts = inl(ACPI_PMIO_BASE + GPE0_STS(bank));
+ if (sts & mask) {
+ outl(mask, ACPI_PMIO_BASE + GPE0_STS(bank));
+ rc = 1;
+ }
+ } while (sts & mask);
+
+ return rc;
+}
+
+/*
+ * If possible, lock 0xcf9. Once the register is locked, it can't be changed.
+ * This lock is reset on cold boot, hard reset, soft reset and Sx.
+ */
+void pmc_global_reset_lock(void)
+{
+ uintptr_t etr = read_pmc_mmio_bar() + ETR;
+ uint32_t reg;
+
+ reg = read32((void *)etr);
+ if (reg & CF9_LOCK)
+ return;
+ reg |= CF9_LOCK;
+ write32((void *)etr, reg);
+}
+
+/*
+ * Enable or disable global reset. If global reset is enabled, hard reset and
+ * soft reset will trigger global reset, where both host and TXE are reset.
+ * This is cleared on cold boot, hard reset, soft reset and Sx.
+ */
+void pmc_global_reset_enable(bool enable)
+{
+ uintptr_t etr = read_pmc_mmio_bar() + ETR;
+ uint32_t reg;
+
+ reg = read32((void *)etr);
+ reg = enable ? reg | CF9_GLB_RST : reg & ~CF9_GLB_RST;
+ write32((void *)etr, reg);
+}
+
+/*
+ * The PM1 control is set to S5 when vboot requests a reboot because the power
+ * state code above may not have collected its data yet. Therefore, set it to
+ * S5 when vboot requests a reboot. That's necessary if vboot fails in the
+ * resume path and requests a reboot. This prevents a reboot loop where the
+ * error is continually hit on the failing vboot resume path.
+ */
+void vboot_platform_prepare_reboot(void)
+{
+ const uint16_t port = ACPI_PMIO_BASE + PM1_CNT;
+ outl((inl(port) & ~(SLP_TYP)) | (SLP_TYP_S5 << SLP_TYP_SHIFT), port);
+}
+
+void poweroff(void)
+{
+ pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));
+
+ /*
+ * Setting SLP_TYP_S5 in PM1 triggers SLP_SMI, which is handled by SMM
+ * to transition to S5 state. If halt is called in SMM, then it prevents
+ * the SMI handler from being triggered and system never enters S5.
+ */
+ if (!ENV_SMM)
+ halt();
+}
--
To view, visit https://review.coreboot.org/19349
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Gerrit-MessageType: newchange
Gerrit-Change-Id: Ic3d96fc23a98c30e8ea0969a7be09d217eeaa889
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Shaunak Saha <shaunak.saha at intel.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
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