[coreboot-gerrit] Change in coreboot[master]: amd/pi/hudson: Add GPIO get function

[Marc Jones (Code Review)]

Marc Jones has posted comments on this change. ( https://review.coreboot.org/19159 )

Change subject: amd/pi/hudson: Add GPIO get function
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Patch Set 1:

(5 comments)

https://review.coreboot.org/#/c/19159/1/src/southbridge/amd/pi/hudson/Makefile.inc
File src/southbridge/amd/pi/hudson/Makefile.inc:

PS1, Line 42: ramstage-y
> Since the GPIO pin addresses are only defined if CONFIG_SOUTHBRIDGE_AMD_PI_
Done


https://review.coreboot.org/#/c/19159/1/src/southbridge/amd/pi/hudson/gpio.c
File src/southbridge/amd/pi/hudson/gpio.c:

Line 23: 
> Do some validation of the address?
Other coreboot gpio functions don't check. This would only be a partial coverage since there are gaps in the register map. I think you have to use the defines, but if you didn't, you could break lots of things. Also could be different per chipset, so... I'm not opposed, but maybe propose a solution for all gpio_get functions.


PS1, Line 24: *(volatile u32 *) gpio_num
> reg = read32((void *)(uintptr_t)gpio_num);
Done


Line 28: 
> Please remove the blank line.
Done


https://review.coreboot.org/#/c/19159/1/src/southbridge/amd/pi/hudson/gpio.h
File src/southbridge/amd/pi/hudson/gpio.h:

Line 106: #define GPIO_BANK2_CONTROL AMD_SB_ACPI_MMIO_ADDR + 0x1700
> From `checkpatch.pl`:
Done


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Gerrit-MessageType: comment
Gerrit-Change-Id: I8f681865715ab947b525320a6f9fc63af1334b59
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Marc Jones <marc at marcjonesconsulting.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Marc Jones <marc at marcjonesconsulting.com>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd at gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
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