[coreboot-gerrit] Change in coreboot[master]: google/eve: Limit memory SKU 5 to 1600MHz

[Duncan Laurie (Code Review)]

Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/19227 )

Change subject: google/eve: Limit memory SKU 5 to 1600MHz
......................................................................


google/eve: Limit memory SKU 5 to 1600MHz

Due to issues with stability limit the SKU with K4EBE304EB-EGCF
memory to 1600MHz instead of 1866MHz.

BUG=b:37172778
BRANCH=none
TEST=pass stress testing on devices with this memory

Change-Id: I02af7e9c35e2c5b0b85223d58025cbd29841d973
Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
Reviewed-on: https://review.coreboot.org/19227
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
M src/mainboard/google/eve/romstage.c
M src/mainboard/google/eve/spd/spd.c
M src/mainboard/google/eve/spd/spd.h
3 files changed, 18 insertions(+), 6 deletions(-)

Approvals:
  Aaron Durbin: Looks good to me, approved
  build bot (Jenkins): Verified



diff --git a/src/mainboard/google/eve/romstage.c b/src/mainboard/google/eve/romstage.c
index 2378e90..cd8fa08 100644
--- a/src/mainboard/google/eve/romstage.c
+++ b/src/mainboard/google/eve/romstage.c
@@ -18,6 +18,7 @@
 #include <stddef.h>
 #include <fsp/soc_binding.h>
 #include <soc/romstage.h>
+#include <console/console.h>
 #include "spd/spd.h"
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
@@ -46,4 +47,10 @@
 	mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data();
 	mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
 	mem_cfg->MemorySpdDataLen = SPD_LEN;
+
+	/* Limit K4EBE304EB-EGCF memory to 1600MHz for stability */
+	if (mainboard_get_spd_index() == 5) {
+		printk(BIOS_WARNING, "Limiting memory to 1600MHz\n");
+		mem_cfg->DdrFreqLimit = 1600;
+	}
 }
diff --git a/src/mainboard/google/eve/spd/spd.c b/src/mainboard/google/eve/spd/spd.c
index bac5107..2f365a7 100644
--- a/src/mainboard/google/eve/spd/spd.c
+++ b/src/mainboard/google/eve/spd/spd.c
@@ -77,20 +77,24 @@
 	}
 }
 
-uintptr_t mainboard_get_spd_data(void)
+int mainboard_get_spd_index(void)
 {
-	char *spd_file;
-	size_t spd_file_len;
-	int spd_index;
-
 	gpio_t spd_gpios[] = {
 		GPIO_MEM_CONFIG_0,
 		GPIO_MEM_CONFIG_1,
 		GPIO_MEM_CONFIG_2,
 		GPIO_MEM_CONFIG_3,
 	};
+	return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}
 
-	spd_index = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+uintptr_t mainboard_get_spd_data(void)
+{
+	char *spd_file;
+	size_t spd_file_len;
+	int spd_index;
+
+	spd_index = mainboard_get_spd_index();
 	printk(BIOS_INFO, "SPD index %d\n", spd_index);
 
 	/* Load SPD data from CBFS */
diff --git a/src/mainboard/google/eve/spd/spd.h b/src/mainboard/google/eve/spd/spd.h
index 9c2b26b..6d8d0a6 100644
--- a/src/mainboard/google/eve/spd/spd.h
+++ b/src/mainboard/google/eve/spd/spd.h
@@ -30,6 +30,7 @@
 #define  SPD_PART_LEN		18
 #define SPD_MANU_OFF		148
 
+int mainboard_get_spd_index(void);
 uintptr_t mainboard_get_spd_data(void);
 
 #endif

-- 
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Gerrit-MessageType: merged
Gerrit-Change-Id: I02af7e9c35e2c5b0b85223d58025cbd29841d973
Gerrit-PatchSet: 2
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins)