[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Use RTC common code

[Martin Roth (Code Review)]

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/18701 )

Change subject: soc/intel/skylake: Use RTC common code
......................................................................


soc/intel/skylake: Use RTC common code

This patch uses common RTC library to enable
upper 128 byte bank of RTC RAM.

Change-Id: Ibcbaf5061e96a67815116a9f7a03be515997be6d
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
Reviewed-on: https://review.coreboot.org/18701
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Tested-by: build bot (Jenkins)
---
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/bootblock/pch.c
2 files changed, 3 insertions(+), 10 deletions(-)

Approvals:
  Aaron Durbin: Looks good to me, approved
  build bot (Jenkins): Verified



diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index ae86198..e22f1e3 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -52,6 +52,7 @@
 	select SOC_INTEL_COMMON_BLOCK
 	select SOC_INTEL_COMMON_BLOCK_GSPI
 	select SOC_INTEL_COMMON_BLOCK_PCR
+	select SOC_INTEL_COMMON_BLOCK_RTC
 	select SOC_INTEL_COMMON_BLOCK_SA
 	select SOC_INTEL_COMMON_BLOCK_XHCI
 	select SOC_INTEL_COMMON_LPSS_I2C
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index ebd68f1..12ce3d0 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -19,6 +19,7 @@
 #include <device/device.h>
 #include <device/pci_def.h>
 #include <intelblocks/pcr.h>
+#include <intelblocks/rtc.h>
 #include <soc/bootblock.h>
 #include <soc/iomap.h>
 #include <soc/itss.h>
@@ -44,9 +45,6 @@
 
 #define PCR_DMI_LPCIOD		0x2770
 #define PCR_DMI_LPCIOE		0x2774
-
-#define PCR_RTC_CONF		0x3400
-#define PCR_RTC_CONF_UCMOS_EN	0x4
 
 /*
  * Enable Prefetching and Caching.
@@ -247,12 +245,6 @@
 	outw(tcocnt, tcobase + TCO1_CNT);
 }
 
-static void soc_config_rtc(void)
-{
-	/* Enable upper 128 bytes of CMOS */
-	pcr_or32(PID_RTC, PCR_RTC_CONF, PCR_RTC_CONF_UCMOS_EN);
-}
-
 static void enable_heci(void)
 {
 	device_t dev = PCH_DEV_CSE;
@@ -322,7 +314,7 @@
 	/* Set up GPE configuration */
 	pmc_gpe_init();
 
-	soc_config_rtc();
+	enable_rtc_upper_bank();
 
 	enable_heci();
 }

-- 
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Gerrit-MessageType: merged
Gerrit-Change-Id: Ibcbaf5061e96a67815116a9f7a03be515997be6d
Gerrit-PatchSet: 16
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar at intel.com>
Gerrit-Reviewer: Bora Guvendik <bora.guvendik at intel.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi at intel.com>
Gerrit-Reviewer: Shaunak Saha <shaunak.saha at intel.com>
Gerrit-Reviewer: build bot (Jenkins)