[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: Cleanup code by using common FAST_SPI ...
Barnali Sarkar (Code Review)
gerrit at coreboot.org
Mon Apr 3 15:35:34 CEST 2017
Barnali Sarkar has uploaded a new change for review. ( https://review.coreboot.org/19080 )
Change subject: soc/intel/apollolake: Cleanup code by using common FAST_SPI module
......................................................................
soc/intel/apollolake: Cleanup code by using common FAST_SPI module
This patch currently contains the following -
1. Use SOC_INTEL_COMMON_BLOCK_FAST_SPI kconfig for common FAST_SPI code.
2. Perform FAST_SPI programming by calling APIs from common FAST_SPI library.
3. Use common FAST_SPI header file.
Change-Id: Ifd72734dadda541fe4c828e4f1716e532ec69c27
Signed-off-by: Barnali Sarkar <barnali.sarkar at intel.com>
---
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/apollolake/bootblock/bootblock.c
M src/soc/intel/apollolake/chip.c
M src/soc/intel/apollolake/flash_ctrlr.c
M src/soc/intel/apollolake/include/soc/flash_ctrlr.h
M src/soc/intel/apollolake/mmap_boot.c
M src/soc/intel/apollolake/romstage.c
7 files changed, 14 insertions(+), 92 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/19080/1
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index ca8f5d0..37b37a1 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -53,6 +53,7 @@
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_SA
+ select SOC_INTEL_COMMON_BLOCK_FAST_SPI
select SOC_INTEL_COMMON_LPSS_I2C
select SOC_INTEL_COMMON_SMI
select SOC_INTEL_COMMON_SPI_FLASH_PROTECT
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index dc17b15..b56f3cd 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -19,10 +19,10 @@
#include <cpu/x86/mtrr.h>
#include <device/pci.h>
#include <intelblocks/systemagent.h>
+#include <intelblocks/fast_spi.h>
#include <lib.h>
#include <soc/iomap.h>
#include <soc/cpu.h>
-#include <soc/flash_ctrlr.h>
#include <soc/gpio.h>
#include <soc/iosf.h>
#include <soc/mmap_boot.h>
@@ -98,35 +98,6 @@
set_var_mtrr(mtrr, 4ULL*GiB - rom_size, rom_size, MTRR_TYPE_WRPROT);
}
-/*
- * Program temporary BAR for SPI in case any of the stages before ramstage need
- * to access SPI MMIO regs. Ramstage will assign a new BAR during PCI
- * enumeration.
- */
-static void enable_spibar(void)
-{
- device_t dev = PCH_DEV_SPI;
- uint8_t val;
-
- /* Disable Bus Master and MMIO space. */
- val = pci_read_config8(dev, PCI_COMMAND);
- val &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
- pci_write_config8(dev, PCI_COMMAND, val);
-
- /* Program Temporary BAR for SPI */
- pci_write_config32(dev, PCI_BASE_ADDRESS_0,
- PRERAM_SPI_BASE_ADDRESS |
- PCI_BASE_ADDRESS_SPACE_MEMORY);
-
- /* Enable Bus Master and MMIO Space */
- val = pci_read_config8(dev, PCI_COMMAND);
- val |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_write_config8(dev, PCI_COMMAND, val);
-
- /* Initialize SPI to allow BIOS to write/erase on flash. */
- spi_flash_init();
-}
-
static void enable_pmcbar(void)
{
device_t pmc = PCH_DEV_PMC;
@@ -158,7 +129,7 @@
enable_pm_timer_emulation();
- enable_spibar();
+ fast_spi_enable_bar(PRERAM_SPI_BASE_ADDRESS);
cache_bios_region();
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 8aed7b6..c14e862 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -24,6 +24,7 @@
#include <cpu/x86/mp.h>
#include <device/device.h>
#include <device/pci.h>
+#include <intelblocks/fast_spi.h>
#include <fsp/api.h>
#include <fsp/util.h>
#include <romstage_handoff.h>
@@ -577,7 +578,7 @@
*/
static void spi_flash_init_cb(void *unused)
{
- spi_flash_init();
+ fast_spi_flash_init();
}
BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_flash_init_cb, NULL);
diff --git a/src/soc/intel/apollolake/flash_ctrlr.c b/src/soc/intel/apollolake/flash_ctrlr.c
index 95f540c..e4aa78e 100644
--- a/src/soc/intel/apollolake/flash_ctrlr.c
+++ b/src/soc/intel/apollolake/flash_ctrlr.c
@@ -22,7 +22,8 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
-#include <soc/flash_ctrlr.h>
+#include <intelblocks/fast_spi.h>
+#include <intelblocks/fast_spi_def.h>
#include <soc/intel/common/spi_flash.h>
#include <soc/pci_devs.h>
#include <spi_flash.h>
@@ -67,20 +68,6 @@
ctx->hsfsts_on_last_error = 0;
}
-/* Read register from the SPI flash controller. 'reg' is the register offset. */
-static uint32_t _spi_flash_ctrlr_reg_read(struct spi_flash_ctx *ctx,
- uint16_t reg)
-{
- uintptr_t addr = ALIGN_DOWN(ctx->mmio_base + reg, 4);
- return read32((void *)addr);
-}
-
-uint32_t spi_flash_ctrlr_reg_read(uint16_t reg)
-{
- BOILERPLATE_CREATE_CTX(ctx);
- return _spi_flash_ctrlr_reg_read(ctx, reg);
-}
-
/* Write to register in SPI flash controller. 'reg' is the register offset. */
static void _spi_flash_ctrlr_reg_write(struct spi_flash_ctx *ctx, uint16_t reg,
uint32_t val)
@@ -107,7 +94,7 @@
uint32_t ptinx_index = sfdp_reg & SPIBAR_PTINX_IDX_MASK;
_spi_flash_ctrlr_reg_write(ctx, SPIBAR_PTINX,
ptinx_index | SPIBAR_PTINX_HORD_JEDEC);
- return _spi_flash_ctrlr_reg_read(ctx, SPIBAR_PTDATA);
+ return fast_spi_flash_ctrlr_reg_read(SPIBAR_PTDATA);
}
/* Fill FDATAn FIFO in preparation for a write transaction. */
@@ -137,7 +124,7 @@
uint32_t hsfsts = SPIBAR_HSFSTS_W1C_BITS;
/* Set up transaction parameters. */
hsfsts |= hsfsts_cycle & SPIBAR_HSFSTS_FCYCLE_MASK;
- hsfsts |= SPIBAR_HSFSTS_FBDC(len - 1);
+ hsfsts |= SPIBAR_HSFSTS_FDBC(len - 1);
_spi_flash_ctrlr_reg_write(ctx, SPIBAR_FADDR, flash_addr);
_spi_flash_ctrlr_reg_write(ctx, SPIBAR_HSFSTS_CTL,
@@ -156,7 +143,7 @@
{
uint32_t hsfsts;
do {
- hsfsts = _spi_flash_ctrlr_reg_read(ctx, SPIBAR_HSFSTS_CTL);
+ hsfsts = fast_spi_flash_ctrlr_reg_read(SPIBAR_HSFSTS_CTL);
if (hsfsts & SPIBAR_HSFSTS_FCERR) {
ctx->hsfsts_on_last_error = hsfsts;
@@ -186,30 +173,6 @@
unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len)
{
return MIN(buf_len, SPIBAR_FDATA_FIFO_SIZE);
-}
-
-/*
- * Write-protection status for BIOS region (BIOS_CONTROL register):
- * EISS/WPD bits 00 01 10 11
- * -- -- -- --
- * normal mode RO RW RO RO
- * SMM mode RO RW RO RW
- */
-void spi_flash_init(void)
-{
- uint32_t bios_ctl;
-
- BOILERPLATE_CREATE_CTX(ctx);
-
- bios_ctl = pci_read_config32(ctx->pci_dev, SPIBAR_BIOS_CONTROL);
- bios_ctl |= SPIBAR_BIOS_CONTROL_WPD;
- bios_ctl &= ~SPIBAR_BIOS_CONTROL_EISS;
-
- /* Enable Prefetching and caching. */
- bios_ctl |= SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE;
- bios_ctl &= ~SPIBAR_BIOS_CONTROL_CACHE_DISABLE;
-
- pci_write_config32(ctx->pci_dev, SPIBAR_BIOS_CONTROL, bios_ctl);
}
/* Flash device operations. */
diff --git a/src/soc/intel/apollolake/include/soc/flash_ctrlr.h b/src/soc/intel/apollolake/include/soc/flash_ctrlr.h
index 336ce52..276df5c 100644
--- a/src/soc/intel/apollolake/include/soc/flash_ctrlr.h
+++ b/src/soc/intel/apollolake/include/soc/flash_ctrlr.h
@@ -86,9 +86,4 @@
* read from the status register. On error returns -1.
*/
int spi_flash_read_status(uint8_t *status);
-
-/* Read SPI controller register. */
-uint32_t spi_flash_ctrlr_reg_read(uint16_t reg);
-
-void spi_flash_init(void);
#endif
diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c
index 50d0ff0..6fe9cc8 100644
--- a/src/soc/intel/apollolake/mmap_boot.c
+++ b/src/soc/intel/apollolake/mmap_boot.c
@@ -22,7 +22,7 @@
#include <commonlib/region.h>
#include <console/console.h>
#include <fmap.h>
-#include <soc/flash_ctrlr.h>
+#include <intelblocks/fast_spi.h>
#include <soc/mmap_boot.h>
/*
@@ -65,7 +65,7 @@
static void bios_mmap_init(void)
{
- size_t size, start, bios_end, bios_mapped_size;
+ size_t size, start, bios_mapped_size;
uintptr_t base;
size = car_get_var(bios_size);
@@ -73,18 +73,10 @@
/* If bios_size is initialized, then bail out. */
if (size != 0)
return;
-
/*
- * BIOS_BFPREG provides info about BIOS Flash Primary Region
- * Base and Limit.
- * Base and Limit fields are in units of 4KiB.
+ * Returns bios_start and fills in size of the BIOS region.
*/
- uint32_t val = spi_flash_ctrlr_reg_read(SPIBAR_BIOS_BFPREG);
-
- start = (val & SPIBAR_BFPREG_PRB_MASK) * 4 * KiB;
- bios_end = (((val & SPIBAR_BFPREG_PRL_MASK) >>
- SPIBAR_BFPREG_PRL_SHIFT) + 1) * 4 * KiB;
- size = bios_end - start;
+ start = fast_spi_get_bios_region(&size);
/* BIOS region is mapped right below 4G. */
base = 4ULL * GiB - size;
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 0270920..c98df55 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -32,7 +32,6 @@
#include <fsp/memmap.h>
#include <fsp/util.h>
#include <soc/cpu.h>
-#include <soc/flash_ctrlr.h>
#include <soc/intel/common/mrc_cache.h>
#include <soc/iomap.h>
#include <soc/systemagent.h>
--
To view, visit https://review.coreboot.org/19080
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Gerrit-MessageType: newchange
Gerrit-Change-Id: Ifd72734dadda541fe4c828e4f1716e532ec69c27
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Barnali Sarkar <barnali.sarkar at intel.com>
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