[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Enable XHCI clock gate control in ACPI

[Martin Roth (Code Review)]

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/18879 )

Change subject: soc/intel/skylake: Enable XHCI clock gate control in ACPI
......................................................................


soc/intel/skylake: Enable XHCI clock gate control in ACPI

Enable SS link trunk clock gating & D3hot when device enters
D3 state.
Similarly disable SS link trunk clock gating & D3hot when device enters
D0 state

TEST=Build & boot Poppy board. Check working for XHCI wake when DUT
is in S3.

Change-Id: Ida2afa2e5f9404c0c15d7027480a28a003ad9a40
Signed-off-by: Naresh G Solanki <naresh.solanki at intel.com>
Reviewed-on: https://review.coreboot.org/18879
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
M src/soc/intel/skylake/acpi/xhci.asl
1 file changed, 14 insertions(+), 0 deletions(-)

Approvals:
  Aaron Durbin: Looks good to me, approved
  build bot (Jenkins): Verified



diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl
index 96f3b6a..4c6625e 100644
--- a/src/soc/intel/skylake/acpi/xhci.asl
+++ b/src/soc/intel/skylake/acpi/xhci.asl
@@ -93,12 +93,18 @@
 		Offset (0x10),
 		, 16,
 		XMEM, 16,	/* MEM_BASE */
+		Offset (0x50),	/* XHCLKGTEN */
+		, 2,
+		STGE, 1,	/* SS Link Trunk clock gating enable */
 		Offset (0x74),
 		D0D3, 2,	/* POWERSTATE */
 		, 6,
 		PMEE, 1,	/* PME_EN */
 		, 6,
 		PMES, 1,	/* PME_STS */
+		Offset (0xA2),
+		, 2,
+		D3HE, 1,	/* D3_hot_en */
 	}
 
 	OperationRegion (XREG, SystemMemory,
@@ -123,6 +129,10 @@
 		If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) {
 			Return
 		}
+
+		/* Disable d3hot and SS link trunk clock gating */
+		Store(Zero, ^D3HE)
+		Store(Zero, ^STGE)
 
 		/* If device is in D3, set back to D0 */
 		If (LEqual (^D0D3, 3)) {
@@ -178,6 +188,10 @@
 		/* Enable USB2 PHY SUS Well Power Gating in D0/D0i2/D0i3/D3 */
 		Store (3, ^UPSW)
 
+		/* Enable d3hot and SS link trunk clock gating */
+                Store(One, ^D3HE)
+                Store(One, ^STGE)
+
 		/* Now put device in D3 */
 		Store (3, Local0)
 		Store (Local0, ^D0D3)

-- 
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Gerrit-MessageType: merged
Gerrit-Change-Id: Ida2afa2e5f9404c0c15d7027480a28a003ad9a40
Gerrit-PatchSet: 4
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Naresh Solanki <naresh.solanki at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan at intel.com>
Gerrit-Reviewer: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Naresh Solanki <naresh.solanki at intel.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Rajat Jain <rajatja at google.com>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: build bot (Jenkins)