[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Enable XHCI clock gate control in ACPI

[Naresh Solanki (Code Review)]

Naresh Solanki has posted comments on this change. ( https://review.coreboot.org/18879 )

Change subject: soc/intel/skylake: Enable XHCI clock gate control in ACPI
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Patch Set 3:

(1 comment)

https://review.coreboot.org/#/c/18879/3/src/soc/intel/skylake/acpi/xhci.asl
File src/soc/intel/skylake/acpi/xhci.asl:

PS3, Line 133: 		/* Disable d3hot and SS link trunk clock gating */
             : 		Store(Zero, ^D3HE)
             : 		Store(Zero, ^STGE)
> as i know, os may call _PS0 multiple time, which mean you will assign 0 to 
This is recommended implementation & is very well validated.

Kernel calls -> _PS0 -> These bits cleared.
Kernel calls -> _PS3 -> These bits set.


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Gerrit-MessageType: comment
Gerrit-Change-Id: Ida2afa2e5f9404c0c15d7027480a28a003ad9a40
Gerrit-PatchSet: 3
Gerrit-Project: coreboot
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