[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Enable XHCI clock gate control in ACPI

[Naresh Solanki (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change.  Please visit

    https://review.coreboot.org/18879

to look at the new patch set (#3).

Change subject: soc/intel/skylake: Enable XHCI clock gate control in ACPI
......................................................................

soc/intel/skylake: Enable XHCI clock gate control in ACPI

Enable SS link trunk clock gating & D3hot when device enters
D3 state.
Similarly disable SS link trunk clock gating & D3hot when device enters
D0 state

TEST=Build & boot Poppy board. Check working for XHCI wake when DUT
is in S3.

Change-Id: Ida2afa2e5f9404c0c15d7027480a28a003ad9a40
Signed-off-by: Naresh G Solanki <naresh.solanki at intel.com>
---
M src/soc/intel/skylake/acpi/xhci.asl
1 file changed, 14 insertions(+), 0 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/18879/3
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Ida2afa2e5f9404c0c15d7027480a28a003ad9a40
Gerrit-PatchSet: 3
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Naresh Solanki <naresh.solanki at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan at intel.com>
Gerrit-Reviewer: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: Naresh Solanki <naresh.solanki at intel.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Rajat Jain <rajatja at google.com>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: build bot (Jenkins)