[coreboot-gerrit] Change in coreboot[master]: AGESA f14: Fix memory clock register decoding

[Martin Roth (Code Review)]

Martin Roth has posted comments on this change. ( https://review.coreboot.org/19042 )

Change subject: AGESA f14: Fix memory clock register decoding
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Patch Set 3:

Can we add a DDR667_FREQUENCY that sets the value to 4?  It might not be in the BKDG, but if you look in the code for F14h, it's the minimum supported frequency, and it exists in all the tables.

I know for some of the processors around this timeframe, the memory training actually started at 667.

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Gerrit-MessageType: comment
Gerrit-Change-Id: I2dfcf1950883836499ea2ca95f9eb72ccdfb979c
Gerrit-PatchSet: 3
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Kyösti Mälkki <kyosti.malkki at gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins)
Gerrit-HasComments: No