[coreboot-gerrit] Patch merged into coreboot/master: google/reef: Remove setting of GPIO_TIER1_SCI enable bit
gerrit at coreboot.org
gerrit at coreboot.org
Thu Sep 15 01:20:13 CEST 2016
the following patch was just integrated into master:
commit b59991949580f59dbf0907881c7ea70729262e9a
Author: Shaunak Saha <shaunak.saha at intel.com>
Date: Fri Sep 9 15:15:27 2016 -0700
google/reef: Remove setting of GPIO_TIER1_SCI enable bit
This patch removes setting of gpio_tier1_sci_en from mainboard
smihandler code. Gpio_tier1_sci enable bit is set from gpio.asl
now.
BUG=chrome-os-partner:56483
TEST=System resumes from S3 on lidopen, powerbutton and USB wake.
Also from S0iX system is resuming for WIFI wake.
Change-Id: I26fd3fd9fcc83c988bcff1bda4da7a2e3da98ce6
Signed-off-by: Shaunak Saha <shaunak.saha at intel.com>
Reviewed-on: https://review.coreboot.org/16566
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
See https://review.coreboot.org/16566 for details.
-gerrit
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