[coreboot-gerrit] Patch merged into coreboot/master: intel/amenia: Remove setting of GPIO_TIER1_SCI enable bit

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 563de15b8a4aafad162352754975158222f8de6c
Author: Shaunak Saha <shaunak.saha at intel.com>
Date:   Fri Sep 9 14:50:34 2016 -0700

    intel/amenia: Remove setting of GPIO_TIER1_SCI enable bit
    
    This patch removes setting of gpio_tier1_sci_en from mainboard
    smihandler code. Gpio_tier1_sci enable bit is set from gpio.asl
    now.
    
    BUG=chrome-os-partner:56483
    TEST=System resumes from S3 on lidopen, powerbutton and USB wake.
         Also from S0iX system is resuming for WIFI wake.
    
    Change-Id: I066f0907a1c597e6fee09821910c59a8a90cccaa
    Signed-off-by: Shaunak Saha <shaunak.saha at intel.com>
    Reviewed-on: https://review.coreboot.org/16565
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Reviewed-by: Andrey Petrov <andrey.petrov at intel.com>


See https://review.coreboot.org/16565 for details.

-gerrit