[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/apollolake: Update PL1 value in RAPL MMIO register

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 35240ebe3c543e3ea416765d980ba8774d14754d
Author: Sumeet Pawnikar <sumeet.r.pawnikar at intel.com>
Date:   Tue Aug 23 11:20:20 2016 +0530

    soc/intel/apollolake: Update PL1 value in RAPL MMIO register
    
    Due to an incorrect value set for the power limit PL1, the
    system is not able to leverage full TDP capacity. FSP code
    sets the PL1 value as 6W in RAPL MMIO register based on
    fused soc tdp value. This RAPL MMIO register is a physically
    separate instance from RAPL MSR register. This patch sets
    PL1 value to 15W in RAPL MMIO register.
    
    BUG=chrome-os-partner:56524
    TEST=Built, booted on reef and verifed the package power
    with heavy workload.
    
    Change-Id: Ib344247cd8d98ccce7c403e778cd87c13f168ce0
    Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar at intel.com>
    Reviewed-on: https://review.coreboot.org/16595
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See https://review.coreboot.org/16595 for details.

-gerrit