[coreboot-gerrit] New patch to review for coreboot: fsp_broadwell_de: Correct access to SIRQ_CNTL register

[Werner Zeh (werner.zeh@siemens.com)]

Werner Zeh (werner.zeh at siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16534

-gerrit

commit 70930caa61b9a57102395e4250e66dad03f2c52b
Author: Werner Zeh <werner.zeh at siemens.com>
Date:   Thu Sep 8 07:27:29 2016 +0200

    fsp_broadwell_de:  Correct access to SIRQ_CNTL register
    
    The serial IRQ configuration register is only 8 bit wide so switch the
    PCI access from 16 bits to 8 bits.
    
    Change-Id: Ia9fbc02251e00b31440bf103e2afc2ff285b7f2e
    Signed-off-by: Werner Zeh <werner.zeh at siemens.com>
---
 src/soc/intel/fsp_broadwell_de/southcluster.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/intel/fsp_broadwell_de/southcluster.c b/src/soc/intel/fsp_broadwell_de/southcluster.c
index 7024814..7ed8896 100644
--- a/src/soc/intel/fsp_broadwell_de/southcluster.c
+++ b/src/soc/intel/fsp_broadwell_de/southcluster.c
@@ -215,7 +215,7 @@ static void sc_init(struct device *dev)
 		PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
 
 	/* Program Serial IRQ register. */
-	pci_write_config16(dev, 0x64, 0xd0);
+	pci_write_config8(dev, 0x64, 0xd0);
 
 	sc_pirq_init(dev);
 	write_pci_config_irqs();