[coreboot-gerrit] New patch to review for coreboot: northbridge/intel/gm45: transation away from device_t

[Antonello Dettori (dev@dettori.io)]

Antonello Dettori (dev at dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16402

-gerrit

commit f8914b36e15500bf80a1536361261bf9aca35eb2
Author: Furquan Shaikh <furquan at google.com>
Date:   Mon Aug 29 22:51:41 2016 -0700

    northbridge/intel/gm45: transation away from device_t
    
    Replace the use of the old device_t definition inside
    northbridge/intel/gm45.
    
    The patch has been tested both with the arch/io.h definition of device_t
    enabled and disabled in order to ensure compatibility while the
    transaction takes place.
    
    Change-Id: I87754799f922cf241fb456071bac04e6fe1eab34
    Signed-off-by: Antonello Dettori <dev at dettori.io>
---
 src/northbridge/intel/gm45/early_init.c |  2 +-
 src/northbridge/intel/gm45/gm45.h       |  2 +-
 src/northbridge/intel/gm45/igd.c        | 12 ++++++------
 src/northbridge/intel/gm45/iommu.c      |  4 ++--
 src/northbridge/intel/gm45/pcie.c       |  8 ++++----
 5 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c
index ee2a6ec..c2e4aea 100644
--- a/src/northbridge/intel/gm45/early_init.c
+++ b/src/northbridge/intel/gm45/early_init.c
@@ -19,7 +19,7 @@
 
 void gm45_early_init(void)
 {
-	const device_t d0f0 = PCI_DEV(0, 0, 0);
+	const pci_devfn_t d0f0 = PCI_DEV(0, 0, 0);
 
 	/* Setup MCHBAR. */
 	pci_write_config32(d0f0, D0F0_MCHBAR_LO, (uintptr_t)DEFAULT_MCHBAR | 1);
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
index c018321..5a30f87 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
@@ -434,7 +434,7 @@ u32 decode_igd_gtt_size(u32 gsm);
 
 void init_iommu(void);
 
-#if ENV_RAMSTAGE
+#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__)
 #include <device/device.h>
 
 struct acpi_rsdp;
diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c
index dc0cc91..73f7651 100644
--- a/src/northbridge/intel/gm45/igd.c
+++ b/src/northbridge/intel/gm45/igd.c
@@ -30,9 +30,9 @@
 /* The PEG settings have to be set before ASPM is setup on DMI. */
 static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg)
 {
-	const device_t mch_dev	= PCI_DEV(0, 0, 0);
-	const device_t peg_dev	= PCI_DEV(0, 1, 0);
-	const device_t igd_dev	= PCI_DEV(0, 2, 0);
+	const pci_devfn_t mch_dev = PCI_DEV(0, 0, 0);
+	const pci_devfn_t peg_dev = PCI_DEV(0, 1, 0);
+	const pci_devfn_t igd_dev = PCI_DEV(0, 2, 0);
 
 	u16 reg16;
 	u32 reg32;
@@ -110,7 +110,7 @@ static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg)
 
 static void disable_igd(const sysinfo_t *const sysinfo)
 {
-	const device_t mch_dev	= PCI_DEV(0, 0, 0);
+	const pci_devfn_t mch_dev = PCI_DEV(0, 0, 0);
 
 	printk(BIOS_DEBUG, "Disabling IGD.\n");
 
@@ -131,7 +131,7 @@ static void disable_igd(const sysinfo_t *const sysinfo)
 
 void init_igd(const sysinfo_t *const sysinfo)
 {
-	const device_t mch_dev	= PCI_DEV(0, 0, 0);
+	const pci_devfn_t mch_dev = PCI_DEV(0, 0, 0);
 
 	const u8 capid = pci_read_config8(mch_dev, D0F0_CAPID0 + 4);
 	if (!sysinfo->enable_igd || (capid & (1 << (33 - 32))))
@@ -142,7 +142,7 @@ void init_igd(const sysinfo_t *const sysinfo)
 
 void igd_compute_ggc(sysinfo_t *const sysinfo)
 {
-	const device_t mch_dev	= PCI_DEV(0, 0, 0);
+	const pci_devfn_t mch_dev = PCI_DEV(0, 0, 0);
 
 	const u32 capid = pci_read_config32(mch_dev, D0F0_CAPID0 + 4);
 	if (!sysinfo->enable_igd || (capid & (1 << (33 - 32))))
diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c
index 10548f4..98e488c 100644
--- a/src/northbridge/intel/gm45/iommu.c
+++ b/src/northbridge/intel/gm45/iommu.c
@@ -46,7 +46,7 @@ void init_iommu()
 	/* clear GTT */
 	u32 gtt = pci_read_config16(PCI_DEV(0, 0, 0), 0x52);
 	if (gtt & 0x400) { /* VT mode */
-		device_t igd = PCI_DEV(0, 2, 0);
+		pci_devfn_t igd = PCI_DEV(0, 2, 0);
 
 		/* setup somewhere */
 		u8 cmd = pci_read_config8(igd, PCI_COMMAND);
@@ -65,7 +65,7 @@ void init_iommu()
 
 	if (stepping == STEPPING_B3) {
 		MCHBAR8(0xffc) |= 1 << 4;
-		device_t peg = PCI_DEV(0, 1, 0);
+		pci_devfn_t peg = PCI_DEV(0, 1, 0);
 		/* FIXME: proper test? */
 		if (pci_read_config8(peg, PCI_CLASS_REVISION) != 0xff) {
 			int val = pci_read_config32(peg, 0xfc) | (1 << 15);
diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c
index cc1fde7..3f56b94 100644
--- a/src/northbridge/intel/gm45/pcie.c
+++ b/src/northbridge/intel/gm45/pcie.c
@@ -112,8 +112,8 @@ static void init_pcie(const int peg_enabled,
 	u8 tmp8;
 	u16 tmp16;
 	u32 tmp;
-	const device_t mch = PCI_DEV(0, 0, 0);
-	const device_t pciex = PCI_DEV(0, 1, 0);
+	const pci_devfn_t mch = PCI_DEV(0, 0, 0);
+	const pci_devfn_t pciex = PCI_DEV(0, 1, 0);
 
 	printk(BIOS_DEBUG, "PEG x%d %s, SDVO %s\n", peg_x16?16:1,
 		peg_enabled?"enabled":"disabled",
@@ -162,7 +162,7 @@ static void init_pcie(const int peg_enabled,
 static void setup_aspm(const stepping_t stepping, const int peg_enabled)
 {
 	u32 tmp32;
-	const device_t pciex = PCI_DEV(0, 1, 0);
+	const pci_devfn_t pciex = PCI_DEV(0, 1, 0);
 
 	/* Prerequisites for ASPM: */
 	if (peg_enabled) {
@@ -327,7 +327,7 @@ static void setup_rcrb(const int peg_enabled)
 
 void gm45_late_init(const stepping_t stepping)
 {
-	const device_t mch = PCI_DEV(0, 0, 0);
+	const pci_devfn_t mch = PCI_DEV(0, 0, 0);
 	const int peg_enabled = (pci_read_config8(mch, D0F0_DEVEN) >> 1) & 1;
 	const int sdvo_enabled = (MCHBAR16(0x40) >> 8) & 1;
 	const int peg_x16 = (peg_enabled && !sdvo_enabled);