[coreboot-gerrit] New patch to review for coreboot: nb/x4x: Move checkreset before SPD reading

[Arthur Heymans (arthur@aheymans.xyz)]

Arthur Heymans (arthur at aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17661

-gerrit

commit 96a28eca79ed3763a67845bb7f9cf8b36b9d20be
Author: Arthur Heymans <arthur at aheymans.xyz>
Date:   Wed Nov 30 20:37:29 2016 +0100

    nb/x4x: Move checkreset before SPD reading
    
    It makes no sense to read SPDs if the system wil reset anyway.
    
    Change-Id: Id2ad9b04860b3e4939a149eef6b619a496179ff8
    Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
 src/northbridge/intel/x4x/raminit.c      | 33 +++++++++++++++++++++++++++++++
 src/northbridge/intel/x4x/raminit_ddr2.c | 34 --------------------------------
 2 files changed, 33 insertions(+), 34 deletions(-)

diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index 122cab5..436815a 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -316,6 +316,37 @@ static void sdram_detect_ram_speed(struct sysinfo *s)
 	}
 }
 
+static void checkreset_ddr2(void)
+{
+	u8 pmcon2;
+	u8 reset = 0;
+
+	if ((MCHBAR16(SSKPD_MCHBAR) == 0xCAFE)) {
+		printk(BIOS_DEBUG, "Waiting for disks to timeout...\n");
+		mdelay(2000);
+		reset = 1;
+	}
+
+	pmcon2 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
+	if (pmcon2 & 0x80) {
+		pmcon2 &= ~0x80;
+		pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2);
+		reset = 1;
+
+		/* do magic 0xf0 thing. */
+		u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0);
+		pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~(1 << 2));
+		reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0);
+		pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 |  (1 << 2));
+	}
+	if (reset) {
+		printk(BIOS_DEBUG, "Reset...\n");
+		outb(0xe, 0xcf9);
+		asm ("hlt");
+	}
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2 | 0x80);
+}
+
 /**
  * @param boot_path: 0 = normal, 1 = reset, 2 = resume from s3
  */
@@ -328,6 +359,8 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
 
 	pci_write_config8(PCI_DEV(0,0,0), 0xdf, 0xff);
 
+	checkreset_ddr2();
+
 	memset(&s, 0, sizeof(struct sysinfo));
 
 	s.boot_path = boot_path;
diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c
index bfc918e..41701ff 100644
--- a/src/northbridge/intel/x4x/raminit_ddr2.c
+++ b/src/northbridge/intel/x4x/raminit_ddr2.c
@@ -254,37 +254,6 @@ static void clkcross_ddr2(struct sysinfo *s)
 	MCHBAR32(0x70c) = clkxtab[i][j][12];
 }
 
-static void checkreset_ddr2(struct sysinfo *s)
-{
-	u8 pmcon2;
-	u8 reset = 0;
-
-	if ((MCHBAR16(SSKPD_MCHBAR) == 0xCAFE)) {
-		printk(BIOS_DEBUG, "Waiting for disks to timeout...\n");
-		mdelay(2000);
-		reset = 1;
-	}
-
-	pmcon2 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
-	if (pmcon2 & 0x80) {
-		pmcon2 &= ~0x80;
-		pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2);
-		reset = 1;
-
-		/* do magic 0xf0 thing. */
-		u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0);
-		pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~(1 << 2));
-		reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0);
-		pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 |  (1 << 2));
-	}
-	if (reset) {
-		printk(BIOS_DEBUG, "Reset...\n");
-		outb(0xe, 0xcf9);
-		asm ("hlt");
-	}
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2 | 0x80);
-}
-
 static void setioclk_ddr2(struct sysinfo *s)
 {
 	MCHBAR32(0x1bc) = 0x08060402;
@@ -1862,9 +1831,6 @@ void raminit_ddr2(struct sysinfo *s)
 	// Select timings based on SPD info
 	sdram_detect_smallest_params2(s);
 
-	// Reset if required
-	checkreset_ddr2(s);
-
 	// Clear self refresh
 	MCHBAR32(0xf14) = MCHBAR32(0xf14) | 0x3;