[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/skylake: Fix top_of_ram calculation

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 721d1b30907d379b1d1cb095f4157229fcedd433
Author: Naresh G Solanki <naresh.solanki at intel.com>
Date:   Wed Nov 16 21:32:04 2016 +0530

    soc/intel/skylake: Fix top_of_ram calculation
    
    FSP 2.0 implementation conditionally sets PMRR base based on
    EnableC6Dram UPD. Therefore, handle the case of the PMRR base not being
    set since FSP 2.0 changed behavior from FSP 1.1 implementation.
    
    If prmrr base is non-zero value, then top_of_ram is prmrr base.
    
    If Probeless trace is enabled, then deduct trace memory size from
    calculated top_of_ram.
    
    Change-Id: I2633bf78705e36b241668a313d215d0455fba607
    Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
    Signed-off-by: Naresh G Solanki <naresh.solanki at intel.com>
    Reviewed-on: https://review.coreboot.org/17554
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See https://review.coreboot.org/17554 for details.

-gerrit