[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/skylake: Disable Legacy PME for Root ports

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit eedf6d8aa81e85b52d3c150dc992cbfb3077988d
Author: Naresh G Solanki <naresh.solanki at intel.com>
Date:   Wed Nov 16 21:27:38 2016 +0530

    soc/intel/skylake: Disable Legacy PME for Root ports
    
    Legacy PME are enabled by default in FSP UPD region.
    When Legacy PME is enabled, then an SCI is generated and should be
    handled by OS and BIOS/Coreboot in collboration. OS requires some
    ACPI methods (eg _L69) which help to determine the wake source and also
    to clear some registers. But this infrastructure is not present as of
    now in coreboot and also linux handles PMEs natively.
    
    Hence the SCI was never handled by OS and the status bits were never
    cleared i.e., PCI_EXP_STS.
    
    For this reason the level triggered SCI will remain active and the
    system will wake up as soon as it enters S3.
    
    To fix this, diabled Legacy PME (PmSci for Root ports).
    
    Change-Id: I61317eb45305bdb14be3cc1a54fd9961d6ed593e
    Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
    Signed-off-by: Naresh G Solanki <naresh.solanki at intel.com>
    Reviewed-on: https://review.coreboot.org/17553
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See https://review.coreboot.org/17553 for details.

-gerrit