[coreboot-gerrit] Patch merged into coreboot/master: nb/intel/sandybridge/raminit: Support CL > 11
gerrit at coreboot.org
gerrit at coreboot.org
Tue Nov 29 17:16:19 CET 2016
the following patch was just integrated into master:
commit 2966c9958985ed5a856f9aa6cfdb6dfa45ea8bf9
Author: Patrick Rudolph <siro at das-labor.org>
Date: Sat Nov 19 15:46:42 2016 +0100
nb/intel/sandybridge/raminit: Support CL > 11
The code won't allow anything beyond CL11 due to short
CAS Latency mask and a bug in mr0 which had the wrong
bit set for CL > 11.
Increase the CAS bitmask, fix the mr0 reg to allow CAS Latencies
from CL 5 to CL 18.
Use defines instead of hardcoding min and max CAS latencies.
Tested on X220 with two 1866 MHz, CL13 memories
Tested-By: Nicola Corna <nicola at corna.info>
Change-Id: I576ee20a923fd63d360a6a8e86c675dd069d53d6
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
Reviewed-on: https://review.coreboot.org/17502
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
See https://review.coreboot.org/17502 for details.
-gerrit
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