[coreboot-gerrit] Patch set updated for coreboot: sb/intel/lynxpoint: enumerate missing USB ports in ACPI

[Matt DeVillier (matt.devillier@gmail.com)]

Matt DeVillier (matt.devillier at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17539

-gerrit

commit b87fb01f91266e478b123f71da3865402c8308f6
Author: CoolStar <coolstarorganization at gmail.com>
Date:   Thu Jul 14 12:42:11 2016 -0700

    sb/intel/lynxpoint: enumerate missing USB ports in ACPI
    
    Lynxpoint supports up to 8 USB 2.0 ports on the EHCI controller,
    and up to 8 USB 2.0 ports plus 4 USB 3.0 ports on the XHCI controller.
    Add missing port names to enable addition of board-specific details for
    each utilized port (which will be added in subsequent commits).
    
    ref: Mobile 4th Generation Intel Core Processor Family I/O
    datasheet, Feb 2013, rev 003
    
    Change-Id: Ic90c956647f11bf4ebaf174d539a1a8b3255766b
    Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
---
 src/southbridge/intel/lynxpoint/acpi/usb.asl | 20 ++++++++++++++------
 1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/src/southbridge/intel/lynxpoint/acpi/usb.asl b/src/southbridge/intel/lynxpoint/acpi/usb.asl
index b02cbfe..021c083 100644
--- a/src/southbridge/intel/lynxpoint/acpi/usb.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/usb.asl
@@ -56,6 +56,8 @@ Device (EHCI)
 		Device (PRT4) { Name (_ADR, 4) } // USB Port 3
 		Device (PRT5) { Name (_ADR, 5) } // USB Port 4
 		Device (PRT6) { Name (_ADR, 6) } // USB Port 5
+		Device (PRT7) { Name (_ADR, 7) } // USB Port 6
+                Device (PRT8) { Name (_ADR, 8) } // USB Port 7
 	}
 }
 
@@ -394,11 +396,17 @@ Device (XHCI)
 		Name (_ADR, 0x00000000)
 
 		// How many are there?
-		Device (PRT1) { Name (_ADR, 1) } // USB Port 0
-		Device (PRT2) { Name (_ADR, 2) } // USB Port 1
-		Device (PRT3) { Name (_ADR, 3) } // USB Port 2
-		Device (PRT4) { Name (_ADR, 4) } // USB Port 3
-		Device (PRT5) { Name (_ADR, 5) } // USB Port 4
-		Device (PRT6) { Name (_ADR, 6) } // USB Port 5
+		Device (PRT1) { Name (_ADR, 1) } // USB 2.0 Port 0
+		Device (PRT2) { Name (_ADR, 2) } // USB 2.0 Port 1
+		Device (PRT3) { Name (_ADR, 3) } // USB 2.0 Port 2
+		Device (PRT4) { Name (_ADR, 4) } // USB 2.0 Port 3
+		Device (PRT5) { Name (_ADR, 5) } // USB 2.0 Port 4
+		Device (PRT6) { Name (_ADR, 6) } // USB 2.0 Port 5
+		Device (PRT7) { Name (_ADR, 7) } // USB 2.0 Port 6
+		Device (PRT8) { Name (_ADR, 8) } // USB 2.0 Port 7
+		Device (SSP1) { Name (_ADR, 10) } // USB 3.0 Port 0
+		Device (SSP2) { Name (_ADR, 11) } // USB 3.0 Port 1
+		Device (SSP3) { Name (_ADR, 12) } // USB 3.0 Port 2
+		Device (SSP4) { Name (_ADR, 13) } // USB 3.0 Port 3
 	}
 }