[coreboot-gerrit] New patch to review for coreboot: intel/sch: Remove explicit PCI MMCONF access

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17529

-gerrit

commit d20ae8cabdd201842efd7b75faffc4c787364c5b
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Fri Jul 26 08:53:59 2013 +0300

    intel/sch: Remove explicit PCI MMCONF access
    
    MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access
    being non-atomic, and we are in interrupt handler here.
    
    Change-Id: I943e354af0403e61263f1c780f02c7b463b3fe11
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/soc/intel/sch/smihandler.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/soc/intel/sch/smihandler.c b/src/soc/intel/sch/smihandler.c
index 57eb35c..6982f58 100644
--- a/src/soc/intel/sch/smihandler.c
+++ b/src/soc/intel/sch/smihandler.c
@@ -275,7 +275,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
 	u16 pm1_sts;
 	u32 smi_sts, gpe0_sts, tco_sts;
 
-	pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x48) & 0xfffc;
+	pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x48) & 0xfffc;
 	printk(BIOS_SPEW, "SMI#: pmbase = 0x%04x\n", pmbase);
 
 	/* We need to clear the SMI status registers, or we won't see what's
@@ -325,7 +325,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
 
 		if (tco_sts & (1 << 8)) { // BIOSWR
 			u8 bios_cntl;
-			bios_cntl = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
+			bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
 			if (bios_cntl & 1) {
 				/* BWE is RW, so the SMI was caused by a
 				 * write to BWE, not by a write to the BIOS
@@ -338,7 +338,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
 				 * box.
 				 */
 				printk(BIOS_DEBUG, "Switching back to RO\n");
-				pcie_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
+				pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
 			} /* No else for now? */
 		}
 	}