[coreboot-gerrit] Patch merged into coreboot/master: nb/intel/sandybridge/raminit: Fix CAS Write Latency

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit bec669685cdd77e12cdf8fad2e68d39218cfdba7
Author: Patrick Rudolph <siro at das-labor.org>
Date:   Fri Nov 11 19:17:56 2016 +0100

    nb/intel/sandybridge/raminit: Fix CAS Write Latency
    
    As documented in DDR3 spec for MR2 the CWL is based on DDR frequency.
    There's no to little difference for most memory modules operating at DDR3-1333.
    
    It might fix problems for memory modules that operate at a higher frequency and
    memory modules with low CL values should work even better.
    
    Tested on Lenovo T420 with DDR3-1333 CL9 and DDR3-1600 CL11.
    No regressions found.
    
    Change-Id: Ib90b5de872a219cf80b4976b6dfae6bc02e298f4
    Signed-off-by: Patrick Rudolph <siro at das-labor.org>
    Reviewed-on: https://review.coreboot.org/17389
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Reviewed-by: Martin Roth <martinroth at google.com>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki at gmail.com>


See https://review.coreboot.org/17389 for details.

-gerrit