[coreboot-gerrit] Patch set updated for coreboot: [not for merge]nb/intel/sandybridge/raminit: Fix wr_t for mr0

[Patrick Rudolph (siro@das-labor.org)]

Patrick Rudolph (siro at das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17503

-gerrit

commit 41634cba6f9262ed0c7640c1da37f0b0a29b00d4
Author: Patrick Rudolph <siro at das-labor.org>
Date:   Sat Nov 19 15:50:46 2016 +0100

    [not for merge]nb/intel/sandybridge/raminit: Fix wr_t for mr0
    
    The spec requires to set any value that is equal or greater
    than tWR. Use the next possible value instead of 0, which
    translates to 16 cycles.
    
    Untested.
    
    Change-Id: I7d93eadc46a5a24f6026256bd09f7dc1b5d5b8a9
    Signed-off-by: Patrick Rudolph <siro at das-labor.org>
---
 src/northbridge/intel/sandybridge/raminit.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index b5ecc52..9b250ec 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -1445,7 +1445,7 @@ static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank,
 static u32 make_mr0(ramctr_timing * ctrl, u8 rank)
 {
 	u16 mr0reg, mch_cas, mch_wr;
-	static const u8 mch_wr_t[12] = { 1, 2, 3, 4, 0, 5, 0, 6, 0, 7, 0, 0 };
+	static const u8 mch_wr_t[12] = { 1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0 };
 
 	/* DLL Reset - self clearing - set after CLK frequency has been changed */
 	mr0reg = 0x100;