[coreboot-gerrit] New patch to review for coreboot: intel sandy/ivy: Increase XIP cache with USE_NATIVE_RAMINIT

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17488

-gerrit

commit 69ffcb8515ecdd86a294c2788ba6b9ffb54b85f7
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Fri Nov 18 19:03:29 2016 +0200

    intel sandy/ivy: Increase XIP cache with USE_NATIVE_RAMINIT
    
    Compiled romstage is over 64kiB and exceeded XIP_ROM_SIZE,
    so it was not entirely set WRPROT cacheable.
    
    Reduces first boot raminit (including training) time by 400ms.
    
    Change-Id: I5c4cbf581fc845150f207087c1527338ca364f60
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/cpu/intel/model_206ax/Kconfig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig
index 8f062e5..b954b79 100644
--- a/src/cpu/intel/model_206ax/Kconfig
+++ b/src/cpu/intel/model_206ax/Kconfig
@@ -25,6 +25,10 @@ config BOOTBLOCK_CPU_INIT
 	string
 	default "cpu/intel/model_206ax/bootblock.c"
 
+config XIP_ROM_SIZE
+	hex
+	default 0x20000 if USE_NATIVE_RAMINIT
+
 config SMM_TSEG_SIZE
 	hex
 	default 0x800000