[coreboot-gerrit] Patch set updated for coreboot: riscv: add a variable to control trap management

[Ronald G. Minnich (rminnich@gmail.com)]

Ronald G. Minnich (rminnich at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17404

-gerrit

commit 73736a5d8d08ba07ab78ea84a48e92efbcec279e
Author: Ronald G. Minnich <rminnich at gmail.com>
Date:   Sat Nov 12 07:31:16 2016 -0800

    riscv: add a variable to control trap management
    
    This variable can be set in a debugger (e.g. Spike)
    to finely control which traps go to coreboot and
    which go to the supervisor.
    
    Change-Id: I292264c15f002c41cf8d278354d8f4c0efbd0895
    Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
---
 src/arch/riscv/virtual_memory.c | 26 ++++++++++++++++----------
 1 file changed, 16 insertions(+), 10 deletions(-)

diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c
index 9ee4eba..7047e6a 100644
--- a/src/arch/riscv/virtual_memory.c
+++ b/src/arch/riscv/virtual_memory.c
@@ -23,6 +23,21 @@
 #include <vm.h>
 #include <symbols.h>
 
+/* Delegate controls which traps are delegated to the payload. If you
+ * wish to temporarily disable some or all delegation you can, in a
+ * debugger, set it to a different value (e.g. 0 to have all traps go
+ * to M-mode). In practice, this variable has been a lifesaver.  It is
+ * still not quite determined which delegation might by unallowed by
+ * the spec so for now we enumerate and set them all. */
+static int delegate = 0
+	| (1 << CAUSE_MISALIGNED_FETCH)
+	| (1 << CAUSE_FAULT_FETCH)
+	| (1 << CAUSE_ILLEGAL_INSTRUCTION)
+	| (1 << CAUSE_BREAKPOINT)
+	| (1 << CAUSE_FAULT_LOAD)
+	| (1 << CAUSE_FAULT_STORE)
+	| (1 << CAUSE_USER_ECALL)
+	;
 pte_t* root_page_table;
 
 /* Indent the following text by 2*level spaces */
@@ -297,16 +312,7 @@ void mstatus_init(void)
 	clear_csr(mip, MIP_MSIP);
 	set_csr(mie, MIP_MSIP);
 
-	/* Configure which exception causes are delegated to supervisor mode */
-	set_csr(medeleg,  (1 << CAUSE_MISALIGNED_FETCH)
-			| (1 << CAUSE_FAULT_FETCH)
-			| (1 << CAUSE_ILLEGAL_INSTRUCTION)
-			| (1 << CAUSE_BREAKPOINT)
-			| (1 << CAUSE_FAULT_LOAD)
-			| (1 << CAUSE_FAULT_STORE)
-			| (1 << CAUSE_USER_ECALL)
-	);
-
+	set_csr(medeleg, delegate);
 
 	/* Enable all user/supervisor-mode counters */
 	/* We'll turn these on once lowrisc gets their bitstream up to