[coreboot-gerrit] Patch set updated for coreboot: riscv: add a variable to control trap management
Ronald G. Minnich (rminnich@gmail.com)
gerrit at coreboot.org
Sat Nov 12 19:28:22 CET 2016
Ronald G. Minnich (rminnich at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17404
-gerrit
commit c6949536ce95310dd67e9b145ea368e7a9674b74
Author: Ronald G. Minnich <rminnich at gmail.com>
Date: Sat Nov 12 07:31:16 2016 -0800
riscv: add a variable to control trap management
This variable can be set in a debugger (e.g. Spike)
to finely control which traps go to coreboot and
which go to the supervisor.
Change-Id: I292264c15f002c41cf8d278354d8f4c0efbd0895
Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
---
src/arch/riscv/virtual_memory.c | 24 ++++++++++++++----------
1 file changed, 14 insertions(+), 10 deletions(-)
diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c
index 999d73c..823342c 100644
--- a/src/arch/riscv/virtual_memory.c
+++ b/src/arch/riscv/virtual_memory.c
@@ -23,6 +23,19 @@
#include <vm.h>
#include <symbols.h>
+/* trap_to_coreboot is a debugging aid. It controls which
+ * traps go to coreboot. We do this as a variable so in
+ * in a debugger we can dynamically control which traps go to
+ * coreboot and which traps go to the payload. Once RISCV
+ * is more solid, we will set all traps to go to the payload,
+ * i.e. set this variable to 0. */
+static int trap_to_coreboot = (1 << CAUSE_MISALIGNED_FETCH)
+ | (1 << CAUSE_FAULT_FETCH)
+ | (1 << CAUSE_ILLEGAL_INSTRUCTION)
+ | (1 << CAUSE_BREAKPOINT)
+ | (1 << CAUSE_FAULT_LOAD)
+ | (1 << CAUSE_FAULT_STORE)
+ | (1 << CAUSE_USER_ECALL);
pte_t* root_page_table;
/* Indent the following text by 2*level spaces */
@@ -223,16 +236,7 @@ void mstatus_init(void)
clear_csr(mip, MIP_MSIP);
set_csr(mie, MIP_MSIP);
- /* Configure which exception causes are delegated to supervisor mode */
- set_csr(medeleg, (1 << CAUSE_MISALIGNED_FETCH)
- | (1 << CAUSE_FAULT_FETCH)
- | (1 << CAUSE_ILLEGAL_INSTRUCTION)
- | (1 << CAUSE_BREAKPOINT)
- | (1 << CAUSE_FAULT_LOAD)
- | (1 << CAUSE_FAULT_STORE)
- | (1 << CAUSE_USER_ECALL)
- );
-
+ set_csr(medeleg, trap_to_coreboot);
/* Enable all user/supervisor-mode counters */
/* We'll turn these on once lowrisc gets their bitstream up to
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