[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Set AES and VMX feature registers

[Venkateswarlu V Vinjamuri (venkateswarlu.v.vinjamuri@intel.com)]

Venkateswarlu V Vinjamuri (venkateswarlu.v.vinjamuri at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17396

-gerrit

commit b8de7373f84246b23ee9283d1657a3ae1a3eb826
Author: Nelson, Cole <colex.nelson at intel.com>
Date:   Fri Nov 11 14:17:37 2016 -0800

    soc/intel/apollolake: Set AES and VMX feature registers
    
    Configure MPinit feature registers during boot and s3 resume.
    1. Lock Advanced Encryption Standard (AES-NI) feature register.
    2. Set and lock VMX feature register.
    
    BUG=chrome-os-partner:56922
    BRANCH=None
    
    Change-Id: Id16f62ec4e7463a466c43d67f2b03e07e324fa93
    Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri at intel.com>
---
 src/include/cpu/intel/turbo.h              | 3 +++
 src/soc/intel/apollolake/cpu.c             | 5 +++++
 src/soc/intel/apollolake/include/soc/cpu.h | 2 ++
 3 files changed, 10 insertions(+)

diff --git a/src/include/cpu/intel/turbo.h b/src/include/cpu/intel/turbo.h
index 6626cb1..b5f9b07 100644
--- a/src/include/cpu/intel/turbo.h
+++ b/src/include/cpu/intel/turbo.h
@@ -20,6 +20,9 @@
 #define CPUID_LEAF_PM		6
 #define PM_CAP_TURBO_MODE	(1 << 1)
 
+#define MSR_IA32_FEATURE_CONTROL	0x3a
+#define VMX_OUTSIDE_SMX_FEATURE	4
+#define IA32_FEATURE_CONTROL_LOCK	1
 #define MSR_IA32_MISC_ENABLES	0x1a0
 /* Disable the Monitor Mwait FSM feature */
 #define MONITOR_MWAIT_DIS_MASK	0x40000
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index 6b5dee2..479ebff 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -43,6 +43,11 @@ static const struct reg_script core_msr_script[] = {
 	REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0),
 	/* Disable support for MONITOR and MWAIT instructions */
 	REG_MSR_RMW(MSR_IA32_MISC_ENABLES, ~MONITOR_MWAIT_DIS_MASK, 0),
+	/* Lock Advanced Encryption Standard (AES-NI) feature register */
+	REG_MSR_RMW(MSR_FEATURE_CONFIG, 0, FEATURE_CONFIG_LOCK),
+	/* Set and lock VMX feature register */
+	REG_MSR_RMW(MSR_IA32_FEATURE_CONTROL, 0,
+		VMX_OUTSIDE_SMX_FEATURE + IA32_FEATURE_CONTROL_LOCK),
 	REG_SCRIPT_END
 };
 
diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h
index e94972d..ef6e1c2 100644
--- a/src/soc/intel/apollolake/include/soc/cpu.h
+++ b/src/soc/intel/apollolake/include/soc/cpu.h
@@ -65,6 +65,8 @@ void apollolake_init_cpus(struct device *dev);
 
 #define MSR_PMG_CST_CONFIG_CONTROL	0xe2
 #define MSR_PMG_IO_CAPTURE_BASE	0xe4
+#define MSR_FEATURE_CONFIG	0x13c
+#define FEATURE_CONFIG_LOCK	1
 #define MSR_POWER_CTL	0x1fc
 
 #define MSR_L2_QOS_MASK(reg)		(0xd10 + reg)