[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/common/lpss_i2c: configure buses by rise/fall times

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 2b3e0cdfc4ddefb85e779fa789ba21406a5f76a3
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Nov 9 23:20:30 2016 -0600

    soc/intel/common/lpss_i2c: configure buses by rise/fall times
    
    The default register count calculations are leading to higher
    frequencies than expected. Provide an alternative method for
    calculating the register counts by utilizing the rise and
    fall times of the bus. If the rise time is supplied the
    rise/fall time values are used, but the register overrides
    take precedence over the rise/fall time calculation.  This
    allows platforms to choose whichever method works the best.
    
    BUG=chrome-os-partner:58889
    
    Change-Id: I7747613ce51d8151848acd916c09ae97bfc4b86a
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: https://review.coreboot.org/17350
    Reviewed-by: Furquan Shaikh <furquan at google.com>
    Tested-by: build bot (Jenkins)


See https://review.coreboot.org/17350 for details.

-gerrit