[coreboot-gerrit] New patch to review for coreboot: mainboard/google/snappy: Set PL1 override to 12000mW

[Wisley Chen (wisley.chen@quantatw.com)]

Wisley Chen (wisley.chen at quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17362

-gerrit

commit d9881589ddea01b395b41ee3a17a547f3c34ed30
Author: Wisley Chen <wisley.chen at quantatw.com>
Date:   Thu Nov 10 09:44:13 2016 -0500

    mainboard/google/snappy: Set PL1 override to 12000mW
    
    Snappy is using APL SoC SKU's with 6W TDP max. As Reef,
    the energy calculation is wrong with the current VR solution.
    Experiments show that SoC TDP max (6W) can be reached
    when RAPL PL1 is set to 12W.
    Therefore, we've inserted 12W override after reading the fused value (6W)
    so that the system can reach the right performance level.
    
    BUG=chrome-os-partner:59034
    BRANCH=master
    TEST=emerge-snappy coreboot chromeos-bootimage
    
    Change-Id: Idd702077cd05e2b43823542cb804b2d4b42f7116
    Signed-off-by: Wisley Chen <wisley.chen at quantatw.com>
---
 src/mainboard/google/reef/variants/snappy/devicetree.cb | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb
index 43ec2ed..b4c53ea 100644
--- a/src/mainboard/google/reef/variants/snappy/devicetree.cb
+++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb
@@ -49,6 +49,11 @@ chip soc/intel/apollolake
 	# Enable DPTF
 	register "dptf_enable" = "1"
 
+	# PL1 override 12000 mW: the energy calculation is wrong with the
+	# current VR solution. Experiments show that SoC TDP max (6W) can
+	# be reached when RAPL PL1 is set to 12W.
+	register "tdp_pl1_override_mw" = "12000"
+
 	# Enable Audio Clock and Power gating
 	register "hdaudio_clk_gate_enable" = "1"
 	register "hdaudio_pwr_gate_enable" = "1"