[coreboot-gerrit] New patch to review for coreboot: kblrvp: Add support for Hynix memory
Naresh Solanki (naresh.solanki@intel.com)
gerrit at coreboot.org
Wed Nov 9 16:04:33 CET 2016
Naresh Solanki (naresh.solanki at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17339
-gerrit
commit 08e95598ad4ed189d7f3644fd0cc2f9be78a6f0c
Author: Naresh G Solanki <naresh.solanki at intel.com>
Date: Wed Nov 9 15:24:49 2016 +0530
kblrvp: Add support for Hynix memory
Add support for hynix memory variant of RVP3.
Change-Id: Ic1f8630b36eb131b70c5e3b620957d9602da11ee
Signed-off-by: Naresh G Solanki <naresh.solanki at intel.com>
---
src/mainboard/intel/kblrvp/spd/Makefile.inc | 25 +++++++---------------
.../kblrvp/spd/hynix_dimm_H9CCNNNBJTMLAR.spd.hex | 16 ++++++++++++++
src/mainboard/intel/kblrvp/spd/spd.c | 1 +
src/mainboard/intel/kblrvp/spd/spd.h | 1 +
src/mainboard/intel/kblrvp/spd/spd_util.c | 3 ++-
5 files changed, 28 insertions(+), 18 deletions(-)
diff --git a/src/mainboard/intel/kblrvp/spd/Makefile.inc b/src/mainboard/intel/kblrvp/spd/Makefile.inc
index 77dd16a..83f4831 100644
--- a/src/mainboard/intel/kblrvp/spd/Makefile.inc
+++ b/src/mainboard/intel/kblrvp/spd/Makefile.inc
@@ -18,23 +18,14 @@ romstage-y += spd_util.c
SPD_BIN = $(obj)/spd.bin
-SPD_SOURCES = rvp3 # 0b0000 Dual Channel 4GB
-SPD_SOURCES += empty
-SPD_SOURCES += empty
-SPD_SOURCES += empty
-SPD_SOURCES += empty
-SPD_SOURCES += empty
-SPD_SOURCES += empty
-SPD_SOURCES += empty
-SPD_SOURCES += empty
-SPD_SOURCES += empty
-SPD_SOURCES += empty
-SPD_SOURCES += empty
-SPD_SOURCES += empty
-SPD_SOURCES += empty
-SPD_SOURCES += empty
-SPD_SOURCES += empty
-
+SPD_SOURCES = rvp3 # 0b000 Dual Channel 4GB
+SPD_SOURCES += empty # 1b001
+SPD_SOURCES += empty # 2b010
+SPD_SOURCES += empty # 3b011
+SPD_SOURCES += empty # 4b100
+SPD_SOURCES += empty # 5b101
+SPD_SOURCES += hynix_dimm_H9CCNNNBJTMLAR # 6b110 Dual Channel 8GB
+SPD_SOURCES += empty # 7b111
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
diff --git a/src/mainboard/intel/kblrvp/spd/hynix_dimm_H9CCNNNBJTMLAR.spd.hex b/src/mainboard/intel/kblrvp/spd/hynix_dimm_H9CCNNNBJTMLAR.spd.hex
new file mode 100644
index 0000000..2f66a2a
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/spd/hynix_dimm_H9CCNNNBJTMLAR.spd.hex
@@ -0,0 +1,16 @@
+91 20 F1 03 05 19 05 0B 03 11 01 08 09 00 40 05
+78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00
+00 80 CA FA 00 00 00 A8 00 08 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 AD 00 00 00 55 00 00 00 00 00
+48 39 43 43 4E 4E 4E 42 4A 54 4D 4C 41 52 2D 4E
+55 44 00 00 80 AD 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/intel/kblrvp/spd/spd.c b/src/mainboard/intel/kblrvp/spd/spd.c
index fe30621..1abee81 100644
--- a/src/mainboard/intel/kblrvp/spd/spd.c
+++ b/src/mainboard/intel/kblrvp/spd/spd.c
@@ -49,6 +49,7 @@ static void mainboard_print_spd_info(uint8_t spd[])
printk(BIOS_INFO, "DDR3\n");
break;
case SPD_DRAM_LPDDR3:
+ case SPD_DRAM_LPDDR3_INTEL:
printk(BIOS_INFO, "LPDDR3\n");
break;
default:
diff --git a/src/mainboard/intel/kblrvp/spd/spd.h b/src/mainboard/intel/kblrvp/spd/spd.h
index 6199fb5..a9f8645 100644
--- a/src/mainboard/intel/kblrvp/spd/spd.h
+++ b/src/mainboard/intel/kblrvp/spd/spd.h
@@ -26,6 +26,7 @@
#define SPD_DRAM_TYPE 2
#define SPD_DRAM_DDR3 0x0B
#define SPD_DRAM_LPDDR3 0x0F
+#define SPD_DRAM_LPDDR3_INTEL 0xF1
#define SPD_DENSITY_BANKS 4
#define SPD_ADDRESSING 5
#define SPD_ORGANIZATION 7
diff --git a/src/mainboard/intel/kblrvp/spd/spd_util.c b/src/mainboard/intel/kblrvp/spd/spd_util.c
index dc042d4..20463a5 100644
--- a/src/mainboard/intel/kblrvp/spd/spd_util.c
+++ b/src/mainboard/intel/kblrvp/spd/spd_util.c
@@ -20,6 +20,7 @@
#include <soc/pei_data.h>
#include <soc/pei_wrapper.h>
#include "boardid.h"
+#include "../board_id.h"
#include "spd.h"
void mainboard_fill_dq_map_data(void *dq_map_ptr)
@@ -65,7 +66,7 @@ uintptr_t mainboard_get_spd_data(void)
int spd_index, spd_span;
size_t spd_file_len;
- spd_index = 0;
+ spd_index = (get_board_id() >> 5) & 0xF;
printk(BIOS_INFO, "SPD index %d\n", spd_index);
/* Load SPD data from CBFS */
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