[coreboot-gerrit] Patch merged into coreboot/master: rockchip/rk3399: sdram: Fix data training function

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit f435f92654a18860814187a029657755f1c1d187
Author: Lin Huang <hl at rock-chips.com>
Date:   Sun Oct 9 09:37:10 2016 +0800

    rockchip/rk3399: sdram: Fix data training function
    
    1. Update write leveling value to 0x200.
    When the wrdqs slave delay is changed to 0x200, the phase between the
    dqs and the clock is 0 degrees. The pcb layout can make sure the tDQSS
    timing is smaller than 0.25tck, so this value is useful for both higher
    and lower frequencies.
    
    2. Disable read leveling for LPDDR3.
    The read leveling result is unreliable - the value is not in the middle
    of the read eye. To fix this, disable read leveling and fix the read
    DQSn slave delay setting for DQn to 0x080 (1/4 cycle delay of the
    input signal).
    
    BUG=None
    BRANCH=None
    TEST=Boot from kevin; Check by shmoo read eye and stability test, that
    the updated value of 0x80 is better.
    
    Change-Id: Ia72b601d9bf4e34ba1b0b4584b2c5c3ce9dafbd4
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 37e8dfe783db3ce71aa026b4609ed0bfa16db06f
    Original-Change-Id: I2a5d40c0348449b2a7c609c1db65da4ed5f1c09f
    Original-Signed-off-by: Lin Huang <hl at rock-chips.com>
    Original-Signed-off-by: Jeff Chen <cym at rock-chips.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/396598
    Original-Commit-Ready: Douglas Anderson <dianders at chromium.org>
    Original-Reviewed-by: Derek Basehore <dbasehore at chromium.org>
    Reviewed-on: https://review.coreboot.org/17105
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martinroth at google.com>


See https://review.coreboot.org/17105 for details.

-gerrit