[coreboot-gerrit] New patch to review for coreboot: skylake: Add Audio DSP device

[Duncan Laurie (dlaurie@google.com)]

Duncan Laurie (dlaurie at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14993

-gerrit

commit 7f6676642a08542bd248e1d3b412862dba20115b
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue May 10 15:42:42 2016 -0700

    skylake: Add Audio DSP device
    
    Add the Audio DSP device for skylake as a PCI driver with a static
    scan_bus handler so generic devices can be declared under it.
    
    This is for devices like the Maxim 98357A which is connected on the
    I2S bus for data but has no control channel bus and instead just has
    a GPIO for channel selection and power down control and needs to
    describe that GPIO connection to the OS via ACPI.
    
    Change-Id: Iae02132ff9c510562483108ab280323f78873afd
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/soc/intel/skylake/Makefile.inc           |  1 +
 src/soc/intel/skylake/dsp.c                  | 33 ++++++++++++++++++++++++++++
 src/soc/intel/skylake/include/soc/pci_devs.h |  4 ++++
 3 files changed, 38 insertions(+)

diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index f835282..e22214f 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -34,6 +34,7 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
 ramstage-y += chip.c
 ramstage-y += cpu.c
 ramstage-y += cpu_info.c
+ramstage-y += dsp.c
 ramstage-y += elog.c
 ramstage-y += finalize.c
 ramstage-y += flash_controller.c
diff --git a/src/soc/intel/skylake/dsp.c b/src/soc/intel/skylake/dsp.c
new file mode 100644
index 0000000..13051a0
--- /dev/null
+++ b/src/soc/intel/skylake/dsp.c
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <soc/ramstage.h>
+
+static struct device_operations dsp_dev_ops = {
+	.read_resources		= &pci_dev_read_resources,
+	.set_resources		= &pci_dev_set_resources,
+	.enable_resources	= &pci_dev_enable_resources,
+	.scan_bus		= &scan_static_bus,
+	.ops_pci		= &soc_pci_ops,
+};
+
+static const struct pci_driver skylake_dsp __pci_driver = {
+	.ops	= &dsp_dev_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device = 0x9d70
+};
diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h
index 2dba3de..53dddcb 100644
--- a/src/soc/intel/skylake/include/soc/pci_devs.h
+++ b/src/soc/intel/skylake/include/soc/pci_devs.h
@@ -43,6 +43,10 @@
 #define  SA_DEVFN_IGD		_SA_DEVFN(IGD)
 #define  SA_DEV_IGD		_SA_DEV(IGD)
 
+#define SA_DEV_SLOT_DSP		0x04
+#define  SA_DEVFN_DSP		_SA_DEVFN(DSP)
+#define  SA_DEV_DSP		_SA_DEV(DSP)
+
 /* PCH Devices */
 #define PCH_DEV_SLOT_ISH	0x13
 #define  PCH_DEVFN_ISH		_PCH_DEVFN(ISH, 0)