[coreboot-gerrit] New patch to review for coreboot: [ASL]: Add asl code to enable google ChromeEC.

[Shaunak Saha (shaunak.saha@intel.com)]

Shaunak Saha (shaunak.saha at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14987

-gerrit

commit 13febc2d8cee395759c1be5793b1756218e137be
Author: Shaunak Saha <shaunak.saha at intel.com>
Date:   Fri May 27 01:13:16 2016 -0700

    [ASL]: Add asl code to enable google ChromeEC.
    
    This patch adds asl code to include support for Google ChromeEC.
    We need this to show the battery icon and notifications like charger
    connect/disconnect etc.
    
    BUG = SYSCROS-13310
    TEST = Plug/Unplug AC Adapter multiple times and make sure the battery
    	connected is charging  properly.
    
    Change-Id: Id908f145789402573ea54fc4f15cf7a0e651ebf4
    Signed-off-by: Shaunak Saha <shaunak.saha at intel.com>
---
 src/mainboard/intel/amenia/acpi/ec.asl        | 26 ++++++++++++++++++++++++++
 src/mainboard/intel/amenia/acpi/mainboard.asl | 26 ++++++++++++++++++++++++++
 src/mainboard/intel/amenia/dsdt.asl           | 11 +++++++++++
 src/mainboard/intel/amenia/ec.h               |  4 ++++
 4 files changed, 67 insertions(+)

diff --git a/src/mainboard/intel/amenia/acpi/ec.asl b/src/mainboard/intel/amenia/acpi/ec.asl
new file mode 100644
index 0000000..fe53cb5
--- /dev/null
+++ b/src/mainboard/intel/amenia/acpi/ec.asl
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* mainboard configuration */
+#include "../ec.h"
+
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+
+/* ACPI code for EC functions */
+#include <ec/google/chromeec/acpi/ec.asl>
diff --git a/src/mainboard/intel/amenia/acpi/mainboard.asl b/src/mainboard/intel/amenia/acpi/mainboard.asl
index 09ef9b4..e3f7776 100644
--- a/src/mainboard/intel/amenia/acpi/mainboard.asl
+++ b/src/mainboard/intel/amenia/acpi/mainboard.asl
@@ -16,6 +16,24 @@
  */
 #include <soc/gpio_defs.h>
 
+Scope (\_SB)
+{
+	Device (LID0)
+        {
+                Name (_HID, EisaId ("PNP0C0D"))
+                Method (_LID, 0)
+                {
+                        Return (\_SB.PCI0.LPCB.EC0.LIDS)
+                }
+
+        }
+
+	Device (PWRB)
+        {
+                Name (_HID, EisaId ("PNP0C0C"))
+        }
+}
+
 Scope (\_SB.PCI0.I2C4)
 {
 	/* Standard Mode: HCNT, LCNT, SDA Hold Register */
@@ -91,3 +109,11 @@ Scope (\_SB.PCI0.I2C3)
 		}
 	}
 }
+
+/*
+ * LPC Trusted Platform Module
+ */
+Scope (\_SB.PCI0.LPCB)
+{
+        #include <drivers/pc80/tpm/acpi/tpm.asl>
+}
diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl
index 19e7360..6b4df8f 100644
--- a/src/mainboard/intel/amenia/dsdt.asl
+++ b/src/mainboard/intel/amenia/dsdt.asl
@@ -24,6 +24,12 @@ DefinitionBlock(
 	0x20110725	// OEM revision
 )
 {
+	// global NVS and variables
+        #include <soc/intel/apollolake/acpi/globalnvs.asl>
+
+	// CPU
+        #include <soc/intel/apollolake/acpi/cpu.asl>
+
 	Scope (\_SB) {
 		Device (PCI0)
 		{
@@ -39,4 +45,9 @@ DefinitionBlock(
 
 	#include "acpi/superio.asl"
 
+	// TODO: This actually should be called from soc specific directory
+	// e.g. in skylake it was included in lpc.asl. But right now we cannot do it
+	// as other boards lile reef does not have ec.asl in mainboard yet.
+	// Move it to soc's asl code onve all the mainboards have ec.asl
+	#include "acpi/ec.asl"
 }
diff --git a/src/mainboard/intel/amenia/ec.h b/src/mainboard/intel/amenia/ec.h
index ab8bcba..91890fd 100644
--- a/src/mainboard/intel/amenia/ec.h
+++ b/src/mainboard/intel/amenia/ec.h
@@ -20,6 +20,10 @@
 
 #include <ec/google/chromeec/ec_commands.h>
 
+/* This is the GPE status bit.
+   TODO: Fix this to proper bit matching GPE routing table */
+#define EC_SCI_GPI   15
+
 #define MAINBOARD_EC_SCI_EVENTS \
 	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)        |\
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)          |\