[coreboot-gerrit] New patch to review for coreboot: [ASL]: Add asl code to enable google ChromeEC.
Shaunak Saha (shaunak.saha@intel.com)
gerrit at coreboot.org
Fri May 20 20:14:58 CEST 2016
Shaunak Saha (shaunak.saha at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14928
-gerrit
commit 4fdc076503e896a830867b2b6f88b457cb31700b
Author: Shaunak Saha <shaunak.saha at intel.com>
Date: Thu May 5 17:11:31 2016 -0700
[ASL]: Add asl code to enable google ChromeEC.
This patch adds asl code to include support for Google ChromeEC.
We need this to show the battery icon and notifications like charger
connect/disconnect etc.
BUG = SYSCROS-13310
TEST = Plug/Unplug AC Adapter multiple times and make sure the battery
connected is charging properly.
Change-Id: I51beb701cace34427c2faadfa3436b7e99232c04
Signed-off-by: Shaunak Saha <shaunak.saha at intel.com>
---
src/mainboard/intel/amenia/acpi/ec.asl | 26 ++++++
src/mainboard/intel/amenia/acpi/mainboard.asl | 25 ++++++
src/mainboard/intel/amenia/dsdt.asl | 8 +-
src/mainboard/intel/amenia/ec.h | 4 +
src/soc/intel/apollolake/acpi/cpu.asl | 118 ++++++++++++++++++++++++++
src/soc/intel/apollolake/acpi/globalnvs.asl | 4 +
src/soc/intel/apollolake/acpi/lpc.asl | 25 ++++++
src/soc/intel/apollolake/acpi/southbridge.asl | 21 +++++
src/soc/intel/apollolake/include/soc/nvs.h | 7 +-
9 files changed, 236 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/intel/amenia/acpi/ec.asl b/src/mainboard/intel/amenia/acpi/ec.asl
new file mode 100644
index 0000000..fe53cb5
--- /dev/null
+++ b/src/mainboard/intel/amenia/acpi/ec.asl
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* mainboard configuration */
+#include "../ec.h"
+
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+
+/* ACPI code for EC functions */
+#include <ec/google/chromeec/acpi/ec.asl>
diff --git a/src/mainboard/intel/amenia/acpi/mainboard.asl b/src/mainboard/intel/amenia/acpi/mainboard.asl
index 35043b0..ad8cdae 100644
--- a/src/mainboard/intel/amenia/acpi/mainboard.asl
+++ b/src/mainboard/intel/amenia/acpi/mainboard.asl
@@ -16,6 +16,24 @@
*/
#include <soc/gpio_defs.h>
+Scope (\_SB)
+{
+ Device (LID0)
+ {
+ Name (_HID, EisaId ("PNP0C0D"))
+ Method (_LID, 0)
+ {
+ Return (\_SB.PCI0.LPCB.EC0.LIDS)
+ }
+
+ }
+
+ Device (PWRB)
+ {
+ Name (_HID, EisaId ("PNP0C0C"))
+ }
+}
+
Scope (\_SB.PCI0.I2C4)
{
Device (ETPA)
@@ -79,3 +97,10 @@ Scope (\_SB.PCI0.I2C3)
}
}
}
+/*
+ * LPC Trusted Platform Module
+ */
+Scope (\_SB.PCI0.LPCB)
+{
+ #include <drivers/pc80/tpm/acpi/tpm.asl>
+}
diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl
index 19e7360..d7cb928 100644
--- a/src/mainboard/intel/amenia/dsdt.asl
+++ b/src/mainboard/intel/amenia/dsdt.asl
@@ -24,12 +24,19 @@ DefinitionBlock(
0x20110725 // OEM revision
)
{
+ // global NVS and variables
+ #include <soc/intel/apollolake/acpi/globalnvs.asl>
+
+ // CPU
+ #include <soc/intel/apollolake/acpi/cpu.asl>
+
Scope (\_SB) {
Device (PCI0)
{
#include <soc/intel/apollolake/acpi/northbridge.asl>
#include <soc/intel/apollolake/acpi/southbridge.asl>
}
+
}
/* Mainboard Specific devices */
#include "acpi/mainboard.asl"
@@ -38,5 +45,4 @@ DefinitionBlock(
#include <soc/intel/apollolake/acpi/sleepstates.asl>
#include "acpi/superio.asl"
-
}
diff --git a/src/mainboard/intel/amenia/ec.h b/src/mainboard/intel/amenia/ec.h
index ab8bcba..5aa0802 100644
--- a/src/mainboard/intel/amenia/ec.h
+++ b/src/mainboard/intel/amenia/ec.h
@@ -20,6 +20,10 @@
#include <ec/google/chromeec/ec_commands.h>
+/* This is the GPE status bit.
+ TODO: Fix this to proper bit with GPE routing table */
+#define EC_SCI_GPI 15
+
#define MAINBOARD_EC_SCI_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
diff --git a/src/soc/intel/apollolake/acpi/cpu.asl b/src/soc/intel/apollolake/acpi/cpu.asl
new file mode 100644
index 0000000..a202ceb
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/cpu.asl
@@ -0,0 +1,118 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* These devices are created at runtime */
+External (\_PR.CP00, DeviceObj)
+External (\_PR.CP01, DeviceObj)
+External (\_PR.CP02, DeviceObj)
+External (\_PR.CP03, DeviceObj)
+External (\_PR.CP04, DeviceObj)
+External (\_PR.CP05, DeviceObj)
+External (\_PR.CP06, DeviceObj)
+External (\_PR.CP07, DeviceObj)
+
+/* Notify OS to re-read CPU tables, assuming ^2 CPU count */
+Method (PNOT)
+{
+ If (LGreaterEqual (\PCNT, 2)) {
+ Notify (\_PR.CP00, 0x81) // _CST
+ Notify (\_PR.CP01, 0x81) // _CST
+ }
+ If (LGreaterEqual (\PCNT, 4)) {
+ Notify (\_PR.CP02, 0x81) // _CST
+ Notify (\_PR.CP03, 0x81) // _CST
+ }
+ If (LGreaterEqual (\PCNT, 8)) {
+ Notify (\_PR.CP04, 0x81) // _CST
+ Notify (\_PR.CP05, 0x81) // _CST
+ Notify (\_PR.CP06, 0x81) // _CST
+ Notify (\_PR.CP07, 0x81) // _CST
+ }
+}
+
+/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */
+Method (PPCN)
+{
+ If (LGreaterEqual (\PCNT, 2)) {
+ Notify (\_PR.CP00, 0x80) // _PPC
+ Notify (\_PR.CP01, 0x80) // _PPC
+ }
+ If (LGreaterEqual (\PCNT, 4)) {
+ Notify (\_PR.CP02, 0x80) // _PPC
+ Notify (\_PR.CP03, 0x80) // _PPC
+ }
+ If (LGreaterEqual (\PCNT, 8)) {
+ Notify (\_PR.CP04, 0x80) // _PPC
+ Notify (\_PR.CP05, 0x80) // _PPC
+ Notify (\_PR.CP06, 0x80) // _PPC
+ Notify (\_PR.CP07, 0x80) // _PPC
+ }
+}
+
+/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */
+Method (TNOT)
+{
+ If (LGreaterEqual (\PCNT, 2)) {
+ Notify (\_PR.CP00, 0x82) // _TPC
+ Notify (\_PR.CP01, 0x82) // _TPC
+ }
+ If (LGreaterEqual (\PCNT, 4)) {
+ Notify (\_PR.CP02, 0x82) // _TPC
+ Notify (\_PR.CP03, 0x82) // _TPC
+ }
+ If (LGreaterEqual (\PCNT, 8)) {
+ Notify (\_PR.CP04, 0x82) // _TPC
+ Notify (\_PR.CP05, 0x82) // _TPC
+ Notify (\_PR.CP06, 0x82) // _TPC
+ Notify (\_PR.CP07, 0x82) // _TPC
+ }
+}
+
+/* Return a package containing enabled processor entries */
+Method (PPKG)
+{
+ If (LGreaterEqual (\PCNT, 8)) {
+ Return (Package()
+ {
+ \_PR.CP00,
+ \_PR.CP01,
+ \_PR.CP02,
+ \_PR.CP03,
+ \_PR.CP04,
+ \_PR.CP05,
+ \_PR.CP06,
+ \_PR.CP07
+ })
+ } ElseIf (LGreaterEqual (\PCNT, 4)) {
+ Return (Package ()
+ {
+ \_PR.CP00,
+ \_PR.CP01,
+ \_PR.CP02,
+ \_PR.CP03
+ })
+ } ElseIf (LGreaterEqual (\PCNT, 2)) {
+ Return (Package ()
+ {
+ \_PR.CP00,
+ \_PR.CP01
+ })
+ } Else {
+ Return (Package ()
+ {
+ \_PR.CP00
+ })
+ }
+}
diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl
index 2ef5031..77881ab 100644
--- a/src/soc/intel/apollolake/acpi/globalnvs.asl
+++ b/src/soc/intel/apollolake/acpi/globalnvs.asl
@@ -28,6 +28,10 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
{
/* Nothing here yet, folks */
Offset (0x00),
+ PCNT, 8, // 0x01 - Processor Count
+ PPCM, 8, // 0x02 - Max PPC State
+ LIDS, 8, // 0x03 - LID State
+ PWRS, 8, // 0x04 - AC Power State
/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
Offset (0x100),
diff --git a/src/soc/intel/apollolake/acpi/lpc.asl b/src/soc/intel/apollolake/acpi/lpc.asl
new file mode 100644
index 0000000..6f64f90
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/lpc.asl
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Intel LPC Bus Device - 0:1f.0 */
+
+Device (LPCB)
+{
+ Name(_ADR, 0x001f0000)
+
+ #include "acpi/ec.asl"
+}
diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl
index 0584439..ca5aa32 100644
--- a/src/soc/intel/apollolake/acpi/southbridge.asl
+++ b/src/soc/intel/apollolake/acpi/southbridge.asl
@@ -23,3 +23,24 @@
/* GPIO controller */
#include "gpio.asl"
+
+/* LPC */
+#include "lpc.asl"
+
+Method (_OSC, 4)
+{
+ /* Check for proper GUID */
+ If (LEqual (Arg0, ToUUID ("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
+ {
+ /* Let OS control everything */
+ Return (Arg3)
+ }
+ Else
+ {
+ /* Unrecognized UUID */
+ CreateDWordField (Arg3, 0, CDW1)
+ Or (CDW1, 4, CDW1)
+ Return (Arg3)
+ }
+}
+
diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h
index 8b3a3af..5beea01 100644
--- a/src/soc/intel/apollolake/include/soc/nvs.h
+++ b/src/soc/intel/apollolake/include/soc/nvs.h
@@ -27,8 +27,13 @@
#include <vendorcode/google/chromeos/gnvs.h>
struct global_nvs_t {
+
/* Miscellaneous */
- uint8_t unused[256];
+ u8 pcnt; /* 0x01 - Processor Count */
+ u8 ppcm; /* 0x02 - Max PPC State */
+ u8 lids; /* 0x03 - LID State */
+ u8 pwrs; /* 0x04 - AC Power State */
+ uint8_t unused[252];
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;
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