[coreboot-gerrit] Patch set updated for coreboot: commonlib/lz4: Avoid unaligned memory access on RISC-V

[Jonathan Neuschäfer (j.neuschaefer@gmx.net)]

Jonathan Neuschäfer (j.neuschaefer at gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14983

-gerrit

commit d2708336d2645dc06d03aec17c1cf4085089cc4c
Author: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
Date:   Fri May 27 09:05:02 2016 +0200

    commonlib/lz4: Avoid unaligned memory access on RISC-V
    
    From the User-Level ISA Specification v2.0:
    
       "We do not mandate atomicity for misaligned accesses so simple
        implementations can just use a machine trap and software handler to
        handle misaligned accesses." (— http://riscv.org/specifications/)
    
    Spike traps on unaligned accesses.
    
    Change-Id: Ia57786916f4076cc08513f4e331c2deec9cfa785
    Signed-off-by: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
---
 src/commonlib/lz4_wrapper.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/commonlib/lz4_wrapper.c b/src/commonlib/lz4_wrapper.c
index 772f791..93fa7e8 100644
--- a/src/commonlib/lz4_wrapper.c
+++ b/src/commonlib/lz4_wrapper.c
@@ -63,6 +63,11 @@ static void LZ4_copy8(void *dst, const void *src)
 			: [src]"r"(src), [dst]"r"(dst)
 			: "memory" );
 	#endif
+#elif defined(__riscv__)
+	/* RISC-V implementations may trap on any unaligned access. */
+	int i;
+	for (i = 0; i < 8; i++)
+		((uint8_t *)dst)[i] = ((uint8_t *)src)[i];
 #else
 	*(uint64_t *)dst = *(const uint64_t *)src;
 #endif