[coreboot-gerrit] New patch to review for coreboot: Exynos7: Add DRAM initialization
Stefan Reinauer (stefan.reinauer@coreboot.org)
gerrit at coreboot.org
Thu May 19 20:38:39 CEST 2016
Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14907
-gerrit
commit b8c01b8a862b29556908d9e09309cc262e9e6de4
Author: Akshay Saraswat <akshay.s at samsung.com>
Date: Thu Aug 7 15:18:33 2014 +0530
Exynos7: Add DRAM initialization
Adding LPDDR4 initialization so that it could be used by upcoming
bootloader stages and kernel.
BUG=None
BRANCH=None
TEST=None
Change-Id: I1d05833cd7bbceffddc024488df9516cfc775176
Signed-off-by: Akshay Saraswat <akshay.s at samsung.com>
---
src/soc/samsung/exynos7/Makefile.inc | 1 +
src/soc/samsung/exynos7/bootblock.c | 4 +
src/soc/samsung/exynos7/dmc_init_lpddr4.c | 593 ++++++++
src/soc/samsung/exynos7/include/soc/asp.h | 232 ++++
src/soc/samsung/exynos7/include/soc/dmc.h | 83 ++
src/soc/samsung/exynos7/include/soc/drex.h | 1081 +++++++++++++++
src/soc/samsung/exynos7/include/soc/phy.h | 2033 ++++++++++++++++++++++++++++
7 files changed, 4027 insertions(+)
diff --git a/src/soc/samsung/exynos7/Makefile.inc b/src/soc/samsung/exynos7/Makefile.inc
index 920e86a..5b7427e 100644
--- a/src/soc/samsung/exynos7/Makefile.inc
+++ b/src/soc/samsung/exynos7/Makefile.inc
@@ -25,6 +25,7 @@ INCLUDES += -Isrc/soc/samsung/exynos7/include/
bootblock-y += bootblock.c
bootblock-y += clock.c
bootblock-y += clock_init.c
+bootblock-y += dmc_init_lpddr4.c
bootblock-y += power.c
# ROMSTAGE : Run primitive tests and remaining basic stuff
diff --git a/src/soc/samsung/exynos7/bootblock.c b/src/soc/samsung/exynos7/bootblock.c
index 5aa2e55..108b683 100644
--- a/src/soc/samsung/exynos7/bootblock.c
+++ b/src/soc/samsung/exynos7/bootblock.c
@@ -24,6 +24,7 @@
#include <soc/clock.h>
#include <soc/cpu.h>
+#include <soc/dmc.h>
#include <soc/power.h>
void bootblock_cpu_init(void)
@@ -48,4 +49,7 @@ void bootblock_cpu_init(void)
if (system_clock_init(is_resume))
while(1)
;
+
+ /* Initialize SDRAM */
+ mem_ctrl_init_lpddr4(is_resume);
}
diff --git a/src/soc/samsung/exynos7/dmc_init_lpddr4.c b/src/soc/samsung/exynos7/dmc_init_lpddr4.c
new file mode 100644
index 0000000..1b12007
--- /dev/null
+++ b/src/soc/samsung/exynos7/dmc_init_lpddr4.c
@@ -0,0 +1,593 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <delay.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <types.h>
+#include <delay.h>
+
+#include <soc/asp.h>
+#include <soc/clock.h>
+#include <soc/dmc.h>
+#include <soc/drex.h>
+#include <soc/phy.h>
+#include <soc/power.h>
+
+static volatile asp_regs_t * asp[] = {
+ (volatile asp_regs_t *)EXYNOS7_DMC_ASP0_BASE,
+ (volatile asp_regs_t *)EXYNOS7_DMC_ASP1_BASE,
+ (volatile asp_regs_t *)EXYNOS7_DMC_ASP2_BASE,
+ (volatile asp_regs_t *)EXYNOS7_DMC_ASP3_BASE
+};
+
+static volatile phy_regs_t * phy[] = {
+ (volatile phy_regs_t *)EXYNOS7_DMC_PHY0_BASE,
+ (volatile phy_regs_t *)EXYNOS7_DMC_PHY1_BASE,
+ (volatile phy_regs_t *)EXYNOS7_DMC_PHY2_BASE,
+ (volatile phy_regs_t *)EXYNOS7_DMC_PHY3_BASE
+};
+
+static volatile drex_regs_t * drex[] = {
+ (volatile drex_regs_t *)EXYNOS7_DMC_DREX0_BASE,
+ (volatile drex_regs_t *)EXYNOS7_DMC_DREX1_BASE,
+ (volatile drex_regs_t *)EXYNOS7_DMC_DREX2_BASE,
+ (volatile drex_regs_t *)EXYNOS7_DMC_DREX3_BASE
+};
+
+static volatile vtmon_regs_t * vtmon[] = {
+ (volatile vtmon_regs_t *)EXYNOS7_DMC_VTMON0_BASE,
+ (volatile vtmon_regs_t *)EXYNOS7_DMC_VTMON1_BASE,
+ (volatile vtmon_regs_t *)EXYNOS7_DMC_VTMON2_BASE,
+ (volatile vtmon_regs_t *)EXYNOS7_DMC_VTMON3_BASE
+};
+
+/******************************************************************************
+ *
+ * @fn dmc_reset
+ *
+ * @brief control DRAM reset signal
+ *
+ * @param reset val
+ *
+ * @return none
+ *
+ *****************************************************************************/
+static void dmc_reset(int reset)
+{
+ writel(reset, (void *) (uintptr_t) &vtmon[3]->DRAM_RESET);
+}
+
+/******************************************************************************
+ *
+ * @fn dmc_preset
+ *
+ * @brief prepare DRAM controller & phy before initialization.
+ *
+ * @param channel number
+ *
+ * @return none
+ *
+ *****************************************************************************/
+static void dmc_preset(int ch)
+{
+ drex[ch]->CONCONTROL.dfi_init_start = 0;
+ drex[ch]->CONCONTROL.timeout_level0 = 0xfff;
+ drex[ch]->CONCONTROL.same_dir_prep = 0;
+ drex[ch]->CONCONTROL.io_pd_con = 0;
+ drex[ch]->CONCONTROL.aref_en = 0;
+
+ drex[ch]->MEMCONTROL.sp_en = 0;
+ drex[ch]->MEMCONTROL.pb_ref_en = 0;
+ drex[ch]->MEMCONTROL.dbi_en = 1;
+ drex[ch]->MEMCONTROL.bl = 4;
+ drex[ch]->MEMCONTROL.num_chunk = 0;
+ drex[ch]->MEMCONTROL.num_chip = 1;
+ drex[ch]->MEMCONTROL.mem_width = 1;
+ drex[ch]->MEMCONTROL.mem_type = 8;
+ drex[ch]->MEMCONTROL.add_lat_pall = 0;
+ drex[ch]->MEMCONTROL.dsref_en = 0;
+ drex[ch]->MEMCONTROL.dpwrdn_type = 0;
+ drex[ch]->MEMCONTROL.dpwrdn_en = 0;
+ drex[ch]->MEMCONTROL.clk_stop_en = 0;
+
+ writel(0, (void *) (uintptr_t) &drex[ch]->CGCONTROL);
+
+ drex[ch]->ZQTIMING.t_zqcs = 0x20;
+ drex[ch]->ZQTIMING.t_zqoper = 0x80;
+ drex[ch]->ZQTIMING.t_zqinit = 0x100;
+ drex[ch]->ZQTIMING.t_zqlat = 0x4;
+
+ drex[ch]->TIMINGRFCPB.t_rfcpb0 = 2;
+ drex[ch]->TIMINGRFCPB.t_rfcpb1 = 2;
+
+ drex[ch]->TIMINGAREF.t_refi = 0x5d;
+ drex[ch]->TIMINGAREF.t_refipb = 11;
+
+ writel(0, (void *) (uintptr_t) &drex[ch]->CGCONTROL);
+
+ writel(TIMINGROW1_VAL, (void *) (uintptr_t) &drex[ch]->TIMINGROW1);
+ writel(TIMINGDATA1_VAL, (void *) (uintptr_t) &drex[ch]->TIMINGDATA1);
+ writel(TIMINGPOWER1_VAL, (void *) (uintptr_t) &drex[ch]->TIMINGPOWER1);
+
+ writel(TIMINGROW0_VAL, (void *) (uintptr_t) &drex[ch]->TIMINGROW0);
+ writel(TIMINGDATA0_VAL, (void *) (uintptr_t) &drex[ch]->TIMINGDATA0);
+ writel(TIMINGPOWER0_VAL, (void *) (uintptr_t) &drex[ch]->TIMINGPOWER0);
+
+ drex[ch]->TIMINGSETSW.timing_set_sw_con = 1;
+ drex[ch]->TIMINGSETSW.timing_set_sw = 1;
+
+ drex[ch]->ETCTIMING.t_mrr = 0x2;
+ drex[ch]->ETCTIMING.t_srr = 0x2;
+ drex[ch]->ETCTIMING.t_src = 0x7;
+
+ drex[ch]->RDFETCH0.vref_setting = 0xc8;
+ drex[ch]->RDFETCH0.rd_fetch = 0x2;
+
+ writel(MEMBASECONFIG0_VAL, (void *) (uintptr_t) &asp[ch]->MEMBASECONFIG0);
+ writel(MEMCONFIG0_VAL, (void *) (uintptr_t) &asp[ch]->MEMCONFIG0);
+ writel(MEMCONFIG1_VAL, (void *) (uintptr_t) &asp[ch]->MEMCONFIG1);
+ writel(MEMSIZE0_VAL, (void *) (uintptr_t) &asp[ch]->MEMSIZE0);
+
+ /* No-gate training */
+ phy[ch]->CAL_CON2.ctrl_shgate = 0;
+ phy[ch]->LP_CON0.ctrl_pulld_dqs = 0xf;
+ phy[ch]->CAL_CON2.ctrl_gateadj = 0;
+ phy[ch]->CAL_CON2.ctrl_gateduradj = 0x3;
+ phy[ch]->OFFSETC_CON0.ctrl_offsetc0 = 0;
+ phy[ch]->OFFSETC_CON0.ctrl_offsetc1 = 0;
+ phy[ch]->SHIFTC_CON0.ctrl_shiftc0 = 0;
+ phy[ch]->SHIFTC_CON0.ctrl_shiftc1 = 0;
+
+ phy[ch]->GNR_CON0.ctrl_cmosrcv = 1;
+ phy[ch]->GNR_CON0.ctrl_dfdqs = 1;
+
+ phy[ch]->CAL_CON2.ctrl_readadj = 0;
+ phy[ch]->CAL_CON2.ctrl_readduradj = 3;
+ phy[ch]->CAL_CON2.ctrl_rodt_disable = 1;
+
+ phy[ch]->ZQ_CON0.zq_mode_noterm = 1;
+ phy[ch]->ZQ_CON6.zq_ds1_noterm = 1;
+ phy[ch]->ZQ_CON6.zq_ds0_noterm = 1;
+
+ phy[ch]->GNR_CON0.ctrl_bstlen = 16;
+ phy[ch]->GNR_CON0.ctrl_rdlat = 16;
+ phy[ch]->GNR_CON0.ctrl_wrlat = 8;
+ phy[ch]->GNR_CON0.ctrl_twpre = 0;
+ phy[ch]->GNR_CON0.ctrl_otf_bl = 1;
+ phy[ch]->CAL_CON0.gate_rdchk_en = 1;
+}
+
+/******************************************************************************
+ *
+ * @fn dmc_zq_cal
+ *
+ * @brief do ZQ calibration
+ *
+ * @param channel number, zq enable
+ *
+ * @return none
+ *
+ *****************************************************************************/
+static void dmc_zq_cal(int ch, int enable)
+{
+ if (enable) {
+ phy[ch]->ZQ_CON0.zq_clk_div_en = 1;
+ phy[ch]->ZQ_CON0.zq_manual_mode = 0;
+ phy[ch]->ZQ_CON0.zq_manual_str = 1;
+ } else {
+ phy[ch]->ZQ_CON0.zq_manual_mode = 0;
+ phy[ch]->ZQ_CON0.zq_clk_div_en = 0;
+ }
+}
+
+/******************************************************************************
+ *
+ * @fn dmc_dfi_update
+ *
+ * @brief reset resync
+ *
+ * @param channel number
+ *
+ * @return none
+ *
+ *****************************************************************************/
+static void dmc_dfi_update(int ch)
+{
+ phy[ch]->OFFSETD_CON0.ctrl_resync = 1;
+ phy[ch]->OFFSETD_CON0.ctrl_resync = 0;
+}
+
+/******************************************************************************
+ *
+ * @fn dmc_dfi_mode
+ *
+ * @brief update dfi mode
+ *
+ * @param channel number, mode, ignore_dic val
+ *
+ * @return none
+ *
+ *****************************************************************************/
+static void dmc_dfi_mode(int ch, int mode, int ignore)
+{
+ if (ignore == 1) {
+ drex[ch]->CONCONTROL.ignore_dic = ignore;
+ drex[ch]->CONCONTROL.update_mode = mode;
+ phy[ch]->OFFSETD_CON0.upd_mode = mode;
+ } else {
+ drex[ch]->CONCONTROL.update_mode = mode;
+ phy[ch]->OFFSETD_CON0.upd_mode = mode;
+ drex[ch]->CONCONTROL.ignore_dic = ignore;
+ }
+}
+
+/******************************************************************************
+ *
+ * @fn dmc_mrw_command
+ *
+ * @brief send MRW command
+ *
+ * @param channel number, rank, ma, operation
+ *
+ * @return none
+ *
+ *****************************************************************************/
+static void dmc_mrw_command(unsigned char ch, unsigned char rank,
+ unsigned char ma, unsigned char op)
+{
+ unsigned char bank_bf;
+ unsigned short addr_bf;
+ unsigned char addr_bf_1_0;
+ unsigned char addr_bf_12_10;
+ unsigned char addr_bf_9_2;
+
+ bank_bf = (ma >> 3) & 0x7;
+ addr_bf_12_10 = ma & 0x7;
+ addr_bf_1_0 = ma >> 6;
+ addr_bf_9_2 = op;
+
+ addr_bf = 0;
+ addr_bf = (addr_bf_12_10 << 10) | (addr_bf_9_2 << 2) | (addr_bf_1_0);
+
+ if (rank < 0)
+ writel((DREX_MRW_COMMAND << 24) | (1 << 21)
+ | (bank_bf << 16) | addr_bf,
+ (void *) (uintptr_t) &drex[ch]->DIRECTCMD);
+ else
+ writel((DREX_MRW_COMMAND << 24) | (rank << 20)
+ | (bank_bf << 16) | addr_bf,
+ (void *) (uintptr_t) &drex[ch]->DIRECTCMD);
+}
+
+/******************************************************************************
+ *
+ * @fn dmc_xsref_command
+ *
+ * @brief send XSREF command
+ *
+ * @param channel number, rank
+ *
+ * @return none
+ *
+ *****************************************************************************/
+static void dmc_xsref_command(unsigned char ch, unsigned char rank)
+{
+ if (rank < 0)
+ writel((DREX_REFSX_COMMAND << 24) | (1 << 21),
+ (void *) (uintptr_t) &drex[ch]->DIRECTCMD);
+ else
+ writel((DREX_REFSX_COMMAND << 24) | (rank << 20),
+ (void *) (uintptr_t) &drex[ch]->DIRECTCMD);
+}
+
+/******************************************************************************
+ *
+ * @fn dmc_mpc_command
+ *
+ * @brief send MPC command
+ *
+ * @param channel number, rank, operation
+ *
+ * @return none
+ *
+ *****************************************************************************/
+static void dmc_mpc_command(int ch, int rank, unsigned char op)
+{
+ if (rank < 0)
+ writel((DREX_MPC_COMMAND << 24) | (1 << 21) | (op << 2),
+ (void *) (uintptr_t) &drex[ch]->DIRECTCMD);
+ else
+ writel((DREX_MPC_COMMAND << 24) | (rank << 20) | (op << 2),
+ (void *) (uintptr_t) &drex[ch]->DIRECTCMD);
+}
+
+/******************************************************************************
+ *
+ * @fn dmc_epd_command
+ *
+ * @brief send EPD command
+ *
+ * @param channel number, rank
+ *
+ * @return none
+ *
+ *****************************************************************************/
+static void dmc_epd_command(int ch, int rank)
+{
+ if (rank < 0)
+ writel((DREX_CKEL_COMMAND << 24) | (1 << 21),
+ (void *) (uintptr_t) &drex[ch]->DIRECTCMD);
+ else
+ writel((DREX_CKEL_COMMAND << 24) | (rank << 20),
+ (void *) (uintptr_t) &drex[ch]->DIRECTCMD);
+}
+
+/******************************************************************************
+ *
+ * @fn dmc_xpd_command
+ *
+ * @brief send XPD command
+ *
+ * @param channel, rank
+ *
+ * @return none
+ *
+ *****************************************************************************/
+static void dmc_xpd_command(int ch, int rank)
+{
+ if (rank < 0)
+ writel((DREX_XPD_COMMAND << 24) | (1 << 21),
+ (void *) (uintptr_t) &drex[ch]->DIRECTCMD);
+ else
+ writel((DREX_XPD_COMMAND << 24) | (rank << 20),
+ (void *) (uintptr_t) &drex[ch]->DIRECTCMD);
+}
+
+/******************************************************************************
+ *
+ * @fn dmc_read_dq_cal
+ *
+ * @brief do read DQ calibration
+ *
+ * @param channel, rank
+ *
+ * @return calibration status
+ *
+ *****************************************************************************/
+static int dmc_read_dq_cal(int ch, int rank)
+{
+ phy[ch]->CAL_CON0.fine_train_en = 0;
+
+ phy[ch]->CAL_CON0.rd_cal_mode = 1;
+
+ drex[ch]->INITTRAINCONFIG.init_read_train_chip0 = 1;
+ drex[ch]->INITTRAINCONTROL.init_train_start = 1;
+
+ do {
+ } while (drex[ch]->PHYSTATUS.training_complete != 1);
+
+ drex[ch]->INITTRAINCONFIG.init_read_train_chip0 = 0;
+ drex[ch]->INITTRAINCONTROL.init_train_start = 0;
+
+ return (readl((void *) (uintptr_t) &phy[ch]->CAL_FAIL_STAT0) & 0xff);
+}
+
+/******************************************************************************
+ *
+ * @fn dmc_write_dq_cal
+ *
+ * @brief do write DQ calibration
+ *
+ * @param channel, rank
+ *
+ * @return calibration status
+ *
+ *****************************************************************************/
+static int dmc_write_dq_cal(int ch, int rank)
+{
+ phy[ch]->CAL_CON0.fine_train_en = 0;
+
+ phy[ch]->CAL_CON0.wr_cal_mode = 1;
+
+ drex[ch]->INITTRAINCONFIG.init_write_train_chip0 = 1;
+ drex[ch]->INITTRAINCONFIG.init_write_train_chip1 = 1;
+
+ drex[ch]->INITTRAINCONTROL.init_train_start = 1;
+
+ do {
+ } while (drex[ch]->PHYSTATUS.training_complete != 1);
+
+ drex[ch]->INITTRAINCONFIG.init_write_train_chip0 = 0;
+ drex[ch]->INITTRAINCONFIG.init_write_train_chip1 = 0;
+
+ drex[ch]->INITTRAINCONTROL.init_train_start = 0;
+
+ return (readl((void *) (uintptr_t) &phy[ch]->CAL_FAIL_STAT0) & 0xff);
+}
+
+/******************************************************************************
+ *
+ * @fn mem_ctrl_init_lpddr4
+ *
+ * @brief memory initialization
+ *
+ * @param none
+ *
+ * @return none
+ *
+ *****************************************************************************/
+void mem_ctrl_init_lpddr4(int is_resume)
+{
+ unsigned int val;
+ int channel = 0;
+
+ /* Disable address hash */
+ val = readl((void *) (uintptr_t) CCORE_REMAP);
+ val &= ~0x1;
+ writel(val, (void *) (uintptr_t) CCORE_REMAP);
+
+ /* Set reset signal low */
+ if (!is_resume)
+ dmc_reset(0);
+
+ for (channel = 0; channel < NUM_DMC_CH; channel++) {
+
+ if ((channel == 1) || (channel == 2)) {
+ drex[channel]->CONCONTROL.ca_swap = 1;
+ phy[channel]->CAL_CON0.ca_swap_mode = 1;
+ drex[channel]->MEMCONTROL.mrr_byte = 1;
+ } else {
+ drex[channel]->CONCONTROL.ca_swap = 0;
+ phy[channel]->CAL_CON0.ca_swap_mode = 0;
+ drex[channel]->MEMCONTROL.mrr_byte = 0;
+ }
+
+ dmc_dfi_mode(channel, 0, 1);
+ if (!is_resume) {
+ dmc_epd_command(channel, -1);
+ }
+ }
+
+ udelay(10);
+
+ /* Set reset signal high */
+ if (!is_resume)
+ dmc_reset(1);
+
+ for (channel = 0; channel < NUM_DMC_CH; channel++) {
+ dmc_preset(channel);
+
+ if ((channel == 0) || (channel == 3)) {
+ dmc_zq_cal(channel, 1);
+ while (phy[channel]->ZQ_CON1.zq_done == 0);
+ dmc_zq_cal(channel, 0);
+ }
+
+ dmc_xpd_command(channel, 0);
+ udelay(1);
+ dmc_xpd_command(channel, 1);
+ udelay(1);
+
+ dmc_mpc_command(channel, 0, LPDDR4_MPC1_ZQCAL_START);
+ udelay(1);
+ dmc_mpc_command(channel, 0, LPDDR4_MPC1_ZQCAL_LATCH);
+ udelay(1);
+ dmc_mpc_command(channel, 1, LPDDR4_MPC1_ZQCAL_START);
+ udelay(1);
+ dmc_mpc_command(channel, 1, LPDDR4_MPC1_ZQCAL_LATCH);
+ udelay(1);
+
+ dmc_mrw_command(channel, 0, 13, 0x40);
+ udelay(1);
+ dmc_mrw_command(channel, 1, 13, 0x40);
+ udelay(1);
+
+ dmc_mrw_command(channel, 0, 1, 0x26);
+ udelay(1);
+ dmc_mrw_command(channel, 1, 1, 0x26);
+ udelay(1);
+
+ dmc_mrw_command(channel, 0, 2, 0x12);
+ udelay(1);
+ dmc_mrw_command(channel, 1, 2, 0x12);
+ udelay(1);
+
+ dmc_mrw_command(channel, 0, 3, 0xf1);
+ udelay(1);
+ dmc_mrw_command(channel, 1, 3, 0xf1);
+ udelay(1);
+
+ dmc_mrw_command(channel, 0, 12, 0x5d);
+ udelay(1);
+ dmc_mrw_command(channel, 1, 12, 0x5d);
+ udelay(1);
+
+ dmc_mrw_command(channel, 0, 22, 0x20);
+ udelay(1);
+ dmc_mrw_command(channel, 1, 22, 0x20);
+ udelay(1);
+
+ dmc_mrw_command(channel, 0, 14, 0x4d);
+ udelay(1);
+ dmc_mrw_command(channel, 1, 14, 0x4d);
+ udelay(1);
+
+ dmc_mrw_command(channel, 0, 11, 0x01);
+ udelay(1);
+ dmc_mrw_command(channel, 1, 11, 0x01);
+ udelay(1);
+
+ dmc_mrw_command(channel, 0, 13, 0x00);
+ udelay(1);
+ dmc_mrw_command(channel, 1, 13, 0x00);
+ udelay(1);
+
+ dmc_mrw_command(channel, 0, 13, 0xc0);
+ udelay(1);
+
+ dmc_mrw_command(channel, 1, 13, 0xc0);
+ udelay(1);
+ }
+
+ dmc_driver_freq();
+
+ for (channel = 0; channel < NUM_DMC_CH; channel++) {
+ dmc_dfi_mode(channel, 1, 0);
+
+ drex[channel]->CONCONTROL.dfi_init_start = 1;
+ while (drex[channel]->PHYSTATUS.dfi_init_complete == 0);
+
+ dmc_dfi_update(channel);
+ udelay(1);
+
+ dmc_mrw_command(channel, 0, 32, (unsigned char)0x55);
+ dmc_mrw_command(channel, 1, 32, (unsigned char)0x55);
+ udelay(1);
+
+ dmc_mrw_command(channel, 0, 15, (unsigned char)0x55);
+ udelay(1);
+ dmc_mrw_command(channel, 1, 15, (unsigned char)0x55);
+ udelay(1);
+
+ dmc_mrw_command(channel, 0, 40, (unsigned char)0x55);
+ udelay(1);
+ dmc_mrw_command(channel, 1, 40, (unsigned char)0x55);
+ udelay(1);
+
+ dmc_mrw_command(channel, 0, 20, (unsigned char)0x55);
+ udelay(1);
+ dmc_mrw_command(channel, 1, 20, (unsigned char)0x55);
+ udelay(1);
+
+ dmc_read_dq_cal(channel, 0);
+
+ dmc_write_dq_cal(channel, 0);
+
+ dmc_dfi_update(channel);
+
+ if (is_resume) {
+ dmc_xsref_command(channel, 0);
+ dmc_xsref_command(channel, 1);
+ }
+
+ drex[channel]->CONCONTROL.aref_en = 1;
+ drex[channel]->ALL_INT_INDI.all_init_done = 1;
+ }
+}
diff --git a/src/soc/samsung/exynos7/include/soc/asp.h b/src/soc/samsung/exynos7/include/soc/asp.h
new file mode 100644
index 0000000..fb6b0da
--- /dev/null
+++ b/src/soc/samsung/exynos7/include/soc/asp.h
@@ -0,0 +1,232 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _CPU_SAMSUNG_EXYNOS7_ASP_H_
+#define _CPU_SAMSUNG_EXYNOS7_ASP_H_
+
+typedef volatile unsigned int rw_bf_t;
+typedef const unsigned int ro_bf_t;
+typedef const unsigned int wo_bf_t;
+
+typedef struct {
+ ro_bf_t no_of_regions : ( 3 - 0 + 1 );
+ ro_bf_t reserved_4_7 : ( 7 - 4 + 1 );
+ ro_bf_t address_width : ( 13 - 8 + 1 );
+ ro_bf_t reserved_14_31 : ( 31 - 14 + 1 );
+} asp_tzconfig_t;
+
+typedef struct {
+ rw_bf_t reaction_value : ( 1 - 0 + 1 );
+ ro_bf_t reserved_2_31 : ( 31 - 2 + 1 );
+} asp_tzaction_t;
+
+typedef struct {
+ rw_bf_t lockdown_regions : ( 8 - 0 + 1 );
+ ro_bf_t reserved_9_30 : ( 30 - 9 + 1 );
+ rw_bf_t enable : ( 31 - 31 + 1 );
+} asp_tzldrange_t;
+
+typedef struct {
+ rw_bf_t region_register : ( 0 - 0 + 1 );
+ ro_bf_t reserved_1_31 : ( 31 - 1 + 1 );
+} asp_tzldselect_t;
+
+typedef struct {
+ ro_bf_t status_r0 : ( 0 - 0 + 1 );
+ ro_bf_t overrun_r0 : ( 1 - 1 + 1 );
+ ro_bf_t status_w0 : ( 2 - 2 + 1 );
+ ro_bf_t overrun_w0 : ( 3 - 3 + 1 );
+ ro_bf_t status_r1 : ( 4 - 4 + 1 );
+ ro_bf_t overrun_r1 : ( 5 - 5 + 1 );
+ ro_bf_t status_w1 : ( 6 - 6 + 1 );
+ ro_bf_t overrun_w1 : ( 7 - 7 + 1 );
+ ro_bf_t status_r2 : ( 8 - 8 + 1 );
+ ro_bf_t overrun_r2 : ( 9 - 9 + 1 );
+ ro_bf_t status_w2 : ( 10 - 10 + 1 );
+ ro_bf_t overrun_w2 : ( 11 - 11 + 1 );
+ ro_bf_t status_r3 : ( 12 - 12 + 1 );
+ ro_bf_t overrun_r3 : ( 13 - 13 + 1 );
+ ro_bf_t status_w3 : ( 14 - 14 + 1 );
+ ro_bf_t overrun_w3 : ( 15 - 15 + 1 );
+ ro_bf_t reserved_16_31 : ( 31 - 16 + 1 );
+} asp_tzinitstatus_t;
+
+typedef struct {
+ ro_bf_t int_clear : ( 31 - 0 + 1 );
+} asp_tzinitclear_t;
+
+typedef struct {
+ ro_bf_t fail_addr_low : ( 31 - 0 + 1 );
+} asp_tzfailaddrlowr_t;
+
+typedef struct {
+ ro_bf_t fail_addr_high : ( 2 - 0 + 1 );
+ ro_bf_t reserved_3_31 : ( 31 - 3 + 1 );
+} asp_tzfailaddrhighr_t;
+
+typedef struct {
+ ro_bf_t reserved_0_19 : ( 19 - 0 + 1 );
+ ro_bf_t privileged : ( 20 - 20 + 1 );
+ ro_bf_t nonsecure : ( 21 - 21 + 1 );
+ ro_bf_t reserved_22_23 : ( 23 - 22 + 1 );
+ ro_bf_t write : ( 24 - 24 + 1 );
+ ro_bf_t reserved_25_31 : ( 31 - 25 + 1 );
+} asp_tzfailctrlr_t;
+
+typedef struct {
+ ro_bf_t axid : ( 15 - 0 + 1 );
+ ro_bf_t reserved_16_31 : ( 31 - 16 + 1 );
+} asp_tzfailidr_t;
+
+typedef struct {
+ ro_bf_t fail_addr_low : ( 31 - 0 + 1 );
+} asp_tzfailaddrloww_t;
+
+typedef struct {
+ ro_bf_t fail_addr_high : ( 2 - 0 + 1 );
+ ro_bf_t reserved_3_31 : ( 31 - 3 + 1 );
+} asp_tzfailaddrhighw_t;
+
+typedef struct {
+ ro_bf_t reserved_0_19 : ( 19 - 0 + 1 );
+ ro_bf_t privileged : ( 20 - 20 + 1 );
+ ro_bf_t nonsecure : ( 21 - 21 + 1 );
+ ro_bf_t reserved_22_23 : ( 23 - 22 + 1 );
+ ro_bf_t write : ( 24 - 24 + 1 );
+ ro_bf_t reserved_25_31 : ( 31 - 25 + 1 );
+} asp_tzfailctrlw_t;
+
+typedef struct {
+ ro_bf_t axid : ( 15 - 0 + 1 );
+ ro_bf_t rsvd0 : ( 31 - 16 + 1 );
+} asp_tzfailidw_t;
+
+typedef struct {
+ ro_bf_t reserved_0_15 : ( 15 - 0 + 1 );
+ rw_bf_t base_address_low : ( 31 - 16 + 1 );
+} asp_tzrslow_t;
+
+typedef struct {
+ rw_bf_t base_address_high : ( 2 - 0 + 1 );
+ ro_bf_t reserved_3_31 : ( 31 - 3 + 1 );
+} asp_tzrshigh_t;
+
+typedef struct {
+ ro_bf_t en : ( 0 - 0 + 1 );
+ ro_bf_t reserved_1_3 : ( 3 - 1 + 1 );
+ ro_bf_t size : ( 22 - 4 + 1 );
+ ro_bf_t reserved_23_27 : ( 27 - 23 + 1 );
+ rw_bf_t sp : ( 31 - 28 + 1 );
+} asp_tzrsattr_t;
+
+typedef struct {
+ rw_bf_t int_test_en : ( 0 - 0 + 1 );
+ ro_bf_t reserved_1_31 : ( 31 - 1 + 1 );
+} asp_tzitcrg_t;
+
+typedef struct {
+ ro_bf_t secure_boot_lock : ( 0 - 0 + 1 );
+ ro_bf_t reserved_1_31 : ( 31 - 1 + 1 );
+} asp_tzitip_t;
+
+typedef struct {
+ rw_bf_t itop_int : ( 0 - 0 + 1 );
+ ro_bf_t reserved_1_31 : ( 31 - 1 + 1 );
+} asp_tzitop_t;
+
+typedef struct {
+ rw_bf_t chunk_end : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_15 : ( 15 - 8 + 1 );
+ rw_bf_t chunk_start : ( 23 - 16 + 1 );
+ ro_bf_t reserved_24_31 : ( 31 - 24 + 1 );
+} asp_membaseconfig0_t;
+
+typedef struct {
+ rw_bf_t chunk_end : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_15 : ( 15 - 8 + 1 );
+ rw_bf_t chunk_start : ( 23 - 16 + 1 );
+ ro_bf_t reserved_24_31 : ( 31 - 24 + 1 );
+} asp_membaseconfig1_t;
+
+typedef struct {
+ rw_bf_t chip_bank : ( 3 - 0 + 1 );
+ rw_bf_t chip_row : ( 7 - 4 + 1 );
+ rw_bf_t chip_col : ( 11 - 8 + 1 );
+ rw_bf_t chip_map : ( 15 - 12 + 1 );
+ rw_bf_t bit_sel0 : ( 16 - 16 + 1 );
+ rw_bf_t bit_sel1 : ( 17 - 17 + 1 );
+ rw_bf_t bit_sel_en_0 : ( 18 - 18 + 1 );
+ rw_bf_t bit_sel_en_1 : ( 19 - 19 + 1 );
+ rw_bf_t bank_lsb : ( 22 - 20 + 1 );
+ ro_bf_t reserved_23 : ( 23 - 23 + 1 );
+ rw_bf_t rank_inter_en : ( 24 - 24 + 1 );
+ ro_bf_t reserved_25_31 : ( 31 - 25 + 1 );
+} asp_memconfig0_t;
+
+typedef struct {
+ rw_bf_t chip_bank : ( 3 - 0 + 1 );
+ rw_bf_t chip_row : ( 7 - 4 + 1 );
+ rw_bf_t chip_col : ( 11 - 8 + 1 );
+ rw_bf_t chip_map : ( 15 - 12 + 1 );
+ rw_bf_t bit_sel0 : ( 16 - 16 + 1 );
+ rw_bf_t bit_sel1 : ( 17 - 17 + 1 );
+ rw_bf_t bit_sel_en_0 : ( 18 - 18 + 1 );
+ rw_bf_t bit_sel_en_1 : ( 19 - 19 + 1 );
+ rw_bf_t bank_lsb : ( 22 - 20 + 1 );
+ ro_bf_t reserved_23 : ( 23 - 23 + 1 );
+ rw_bf_t rank_inter_en : ( 24 - 24 + 1 );
+ ro_bf_t reserved_25_31 : ( 31 - 25 + 1 );
+} asp_memconfig1_t;
+
+typedef struct {
+ rw_bf_t chip0_size : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} asp_memsize0_t;
+
+
+typedef struct {
+ asp_tzfailaddrlowr_t TZFAILADDRLOWR;
+ asp_tzfailaddrhighr_t TZFAILADDRHIGHR;
+ asp_tzfailctrlr_t TZFAILCTRLR;
+ asp_tzfailidr_t TZFAILIDR;
+ asp_tzfailaddrloww_t TZFAILADDRLOWW;
+ asp_tzfailaddrhighw_t TZFAILADDRHIGHW;
+ asp_tzfailctrlw_t TZFAILCTRLW;
+ asp_tzfailidw_t TZFAILIDW;
+} asp_tzfail_set_t;
+
+typedef struct {
+ asp_tzrslow_t TZRSLOW;
+ asp_tzrshigh_t TZRSHIGH;
+ asp_tzrsattr_t TZRSATTR;
+ ro_bf_t reserved_0_31;
+} asp_tzrs_set_t;
+
+typedef struct {
+ ro_bf_t reserved_0x0_0xefc[960];
+ asp_membaseconfig0_t MEMBASECONFIG0;
+ asp_membaseconfig1_t MEMBASECONFIG1;
+ ro_bf_t reserved_0x8_0xc[2];
+ asp_memconfig0_t MEMCONFIG0;
+ asp_memconfig1_t MEMCONFIG1;
+ ro_bf_t reserved_0x18_0x1c[2];
+ asp_memsize0_t MEMSIZE0;
+} asp_regs_t;
+
+#endif /* _CPU_SAMSUNG_EXYNOS7_ASP_H_ */
diff --git a/src/soc/samsung/exynos7/include/soc/dmc.h b/src/soc/samsung/exynos7/include/soc/dmc.h
new file mode 100644
index 0000000..cc539bb
--- /dev/null
+++ b/src/soc/samsung/exynos7/include/soc/dmc.h
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _CPU_SAMSUNG_EXYNOS7_DMC_H_
+#define _CPU_SAMSUNG_EXYNOS7_DMC_H_
+
+#define NUM_DMC_CH 4
+#define TIMEOUT 100000
+
+/* Timing Values */
+#define TIMINGROW0_VAL 0x1D2442C7
+#define TIMINGDATA0_VAL 0x2341A350
+#define TIMINGPOWER0_VAL 0x1C1F0233
+#define TIMINGROW1_VAL 0x1D2442C7
+#define TIMINGDATA1_VAL 0x2341A350
+#define TIMINGPOWER1_VAL 0x1C1F0233
+
+/* ASP Values */
+#define MEMBASECONFIG0_VAL 0x00010004
+#define MEMCONFIG0_VAL 0x01302333
+#define MEMCONFIG1_VAL 0x01302333
+#define MEMSIZE0_VAL 0x00000001
+
+/* BLK CCORE*/
+#define CCORE_REMAP (EXYNOS7_SYSREG_BASE + 0x720)
+
+typedef volatile unsigned int rw_bf_t;
+typedef const unsigned int ro_bf_t;
+typedef const unsigned int wo_bf_t;
+
+typedef enum {
+ DREX_MRW_COMMAND = 0x0,
+ DREX_PALL_COMMAND = 0x1,
+ DREX_PRE_COMMAND = 0x2,
+ DREX_MPC_COMMAND = 0x3,
+ DREX_REFS_COMMAND = 0x4,
+ DREX_REFA_COMMAND = 0x5,
+ DREX_CKEL_COMMAND = 0x6,
+ DREX_XPD_COMMAND = 0x7,
+ DREX_REFSX_COMMAND = 0x8,
+ DREX_MRR_COMMAND = 0x9,
+} drex_direct_command_t;
+
+typedef enum {
+ LPDDR4_MPC1_NOP = 0,
+ LPDDR4_MPC1_RD_FIFO = 0x41,
+ LPDDR4_MPC1_RD_DQ_CALIBRATION = 0x43,
+ LPDDR4_MPC1_WR_FIFO = 0x47,
+ LPDDR4_MPC1_START_DQS_OSC = 0x4b,
+ LPDDR4_MPC1_STOP_DQS_OSC = 0x4d,
+ LPDDR4_MPC1_ZQCAL_START = 0x4f,
+ LPDDR4_MPC1_ZQCAL_LATCH = 0x51,
+} lpddr4_mpc_mode_t;
+
+typedef struct {
+ rw_bf_t reset : ( 0 - 0 + 1 );
+ ro_bf_t reserved_1_31 : ( 31 - 1 + 1 );
+} vtmon_dram_reset_t;
+
+typedef struct {
+ ro_bf_t reserved_0x0_0x3c[16];
+ vtmon_dram_reset_t DRAM_RESET;
+} vtmon_regs_t;
+
+void mem_ctrl_init_lpddr4(int is_resume);
+
+#endif /* _CPU_SAMSUNG_EXYNOS7_DMC_H_ */
diff --git a/src/soc/samsung/exynos7/include/soc/drex.h b/src/soc/samsung/exynos7/include/soc/drex.h
new file mode 100644
index 0000000..88a8c38
--- /dev/null
+++ b/src/soc/samsung/exynos7/include/soc/drex.h
@@ -0,0 +1,1081 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _CPU_SAMSUNG_EXYNOS7_DREX_H_
+#define _CPU_SAMSUNG_EXYNOS7_DREX_H_
+
+typedef volatile unsigned int rw_bf_t;
+typedef const unsigned int ro_bf_t;
+typedef const unsigned int wo_bf_t;
+
+typedef struct {
+ rw_bf_t ca_swap : ( 0 - 0 + 1 );
+ ro_bf_t reserved_1_2 : ( 2 - 1 + 1 );
+ rw_bf_t update_mode : ( 3 - 3 + 1 );
+ ro_bf_t reserved_4 : ( 4 - 4 + 1 );
+ rw_bf_t aref_en : ( 5 - 5 + 1 );
+ rw_bf_t io_pd_con : ( 7 - 6 + 1 );
+ ro_bf_t empty : ( 8 - 8 + 1 );
+ ro_bf_t reserved_9_11 : ( 11 - 9 + 1 );
+ rw_bf_t same_dir_prep : ( 12 - 12 + 1 );
+ ro_bf_t reserved_13_15 : ( 15 - 13 + 1 );
+ rw_bf_t timeout_level0 : ( 27 - 16 + 1 );
+ rw_bf_t dfi_init_start : ( 28 - 28 + 1 );
+ ro_bf_t reserved_29_30 : ( 30 - 29 + 1 );
+ rw_bf_t ignore_dic : ( 31 - 31 + 1 );
+} drex_concontrol_t;
+
+typedef struct {
+ rw_bf_t clk_stop_en : ( 0 - 0 + 1 );
+ rw_bf_t dpwrdn_en : ( 1 - 1 + 1 );
+ rw_bf_t dpwrdn_type : ( 3 - 2 + 1 );
+ ro_bf_t reserved_4 : ( 4 - 4 + 1 );
+ rw_bf_t dsref_en : ( 5 - 5 + 1 );
+ rw_bf_t add_lat_pall : ( 7 - 6 + 1 );
+ rw_bf_t mem_type : ( 11 - 8 + 1 );
+ rw_bf_t mem_width : ( 15 - 12 + 1 );
+ rw_bf_t num_chip : ( 17 - 16 + 1 );
+ rw_bf_t num_chunk : ( 19 - 18 + 1 );
+ rw_bf_t bl : ( 22 - 20 + 1 );
+ rw_bf_t dbi_en : ( 23 - 23 + 1 );
+ ro_bf_t reserved_24 : ( 24 - 24 + 1 );
+ rw_bf_t mrr_byte : ( 25 - 25 + 1 );
+ ro_bf_t reserved_26 : ( 26 - 26 + 1 );
+ rw_bf_t pb_ref_en : ( 27 - 27 + 1 );
+ rw_bf_t sp_en : ( 28 - 28 + 1 );
+ rw_bf_t pause_ref_en : ( 29 - 29 + 1 );
+ ro_bf_t reserved_30_31 : ( 31 - 30 + 1 );
+} drex_memcontrol_t;
+
+typedef struct {
+ rw_bf_t busif_rd_cg_en : ( 0 - 0 + 1 );
+ rw_bf_t busif_wr_cg_en : ( 1 - 1 + 1 );
+ rw_bf_t scg_cg_en : ( 2 - 2 + 1 );
+ rw_bf_t mif_cg_en : ( 3 - 3 + 1 );
+ rw_bf_t phy_cg_en : ( 4 - 4 + 1 );
+ rw_bf_t asp_cg_en : ( 5 - 5 + 1 );
+ rw_bf_t scg_wr_cg_en : ( 6 - 6 + 1 );
+ rw_bf_t scg_rd_cg_en : ( 7 - 7 + 1 );
+ rw_bf_t mif_wr_cg_en : ( 8 - 8 + 1 );
+ rw_bf_t mif_rd_cg_en : ( 9 - 9 + 1 );
+ ro_bf_t reserved_10_31 : ( 31 - 10 + 1 );
+} drex_cgcontrol_t;
+
+typedef struct {
+ rw_bf_t cmd_addr : ( 15 - 0 + 1 );
+ rw_bf_t cmd_bank : ( 18 - 16 + 1 );
+ rw_bf_t rsvd2 : ( 19 - 19 + 1 );
+ rw_bf_t cmd_chip : ( 20 - 20 + 1 );
+ rw_bf_t cmd_chip_all : ( 21 - 21 + 1 );
+ ro_bf_t reserved_22_23 : ( 23 - 22 + 1 );
+ rw_bf_t cmd_type : ( 27 - 24 + 1 );
+ ro_bf_t reserved_28_31 : ( 31 - 28 + 1 );
+} drex_directcmd_t;
+
+typedef struct {
+ ro_bf_t reserved_0_15 : ( 15 - 0 + 1 );
+ rw_bf_t port_policy : ( 19 - 16 + 1 );
+ ro_bf_t reserved_20_27 : ( 27 - 20 + 1 );
+ rw_bf_t tp_en : ( 31 - 28 + 1 );
+} drex_prechconfig0_t;
+
+typedef struct {
+ rw_bf_t mem_term_chips : ( 0 - 0 + 1 );
+ rw_bf_t sl_dll_dyn_con : ( 1 - 1 + 1 );
+ rw_bf_t drv_bus_en : ( 2 - 2 + 1 );
+ rw_bf_t fp_resync : ( 3 - 3 + 1 );
+ rw_bf_t dqs_delay : ( 6 - 4 + 1 );
+ rw_bf_t pause_no_relock : ( 7 - 7 + 1 );
+ rw_bf_t reserved_8_11 : ( 11 - 8 + 1 );
+ rw_bf_t rec_gate_cyc : ( 15 - 12 + 1 );
+ ro_bf_t reserved_16_23 : ( 23 - 16 + 1 );
+ rw_bf_t ctrl_pd : ( 24 - 24 + 1 );
+ ro_bf_t reserved_25_28 : ( 28 - 25 + 1 );
+ rw_bf_t ctrl_shgate : ( 29 - 29 + 1 );
+ ro_bf_t reserved_30_31 : ( 31 - 30 + 1 );
+} drex_phycontrol0_t;
+
+typedef struct {
+ rw_bf_t tp_cnt0 : ( 7 - 0 + 1 );
+ rw_bf_t tp_cnt1 : ( 15 - 8 + 1 );
+ rw_bf_t tp_cnt2 : ( 23 - 16 + 1 );
+ rw_bf_t tp_cnt3 : ( 31 - 24 + 1 );
+} drex_prechconfig1_t;
+
+typedef struct {
+ rw_bf_t t_rfcpb0 : ( 5 - 0 + 1 );
+ ro_bf_t rsvd1 : ( 7 - 6 + 1 );
+ rw_bf_t t_rfcpb1 : ( 13 - 8 + 1 );
+ ro_bf_t reserved_14_31 : ( 31 - 14 + 1 );
+} drex_timingrfcpb_t;
+
+typedef struct {
+ rw_bf_t t_zqcs : ( 7 - 0 + 1 );
+ rw_bf_t t_zqoper : ( 17 - 8 + 1 );
+ rw_bf_t t_zqinit : ( 27 - 18 + 1 );
+ rw_bf_t t_zqlat : ( 31 - 28 + 1 );
+} drex_zqtiming_t;
+
+typedef struct {
+ rw_bf_t dpwrdn_cyc : ( 7 - 0 + 1 );
+ ro_bf_t rsvd0 : ( 15 - 8 + 1 );
+ rw_bf_t dsref_cyc : ( 31 - 16 + 1 );
+} drex_pwrdnconfig_t;
+
+typedef struct {
+ rw_bf_t t_refi : ( 15 - 0 + 1 );
+ rw_bf_t t_refipb : ( 31 - 16 + 1 );
+} drex_timingaref_t;
+
+typedef struct {
+ rw_bf_t t_ras : ( 5 - 0 + 1 );
+ rw_bf_t t_rc : ( 11 - 6 + 1 );
+ rw_bf_t t_rcd : ( 15 - 12 + 1 );
+ rw_bf_t t_rp : ( 19 - 16 + 1 );
+ rw_bf_t t_rrd : ( 23 - 20 + 1 );
+ rw_bf_t t_rfc : ( 31 - 24 + 1 );
+} drex_timingrow0_t;
+
+typedef struct {
+ rw_bf_t rl : ( 5 - 0 + 1 );
+ rw_bf_t r_to_w : ( 9 - 6 + 1 );
+ rw_bf_t wl : ( 13 - 10 + 1 );
+ rw_bf_t t_r2r_c2c : ( 15 - 14 + 1 );
+ rw_bf_t t_w2w_c2c : ( 18 - 16 + 1 );
+ rw_bf_t r_to_w_5th : ( 19 - 19 + 1 );
+ rw_bf_t t_rtp : ( 23 - 20 + 1 );
+ rw_bf_t t_wr : ( 27 - 24 + 1 );
+ rw_bf_t t_wtr : ( 31 - 28 + 1 );
+} drex_timingdata0_t;
+
+typedef struct {
+ rw_bf_t t_mrd : ( 3 - 0 + 1 );
+ rw_bf_t t_cke : ( 7 - 4 + 1 );
+ rw_bf_t t_xp : ( 15 - 8 + 1 );
+ rw_bf_t t_xsr : ( 25 - 16 + 1 );
+ rw_bf_t t_faw : ( 31 - 26 + 1 );
+} drex_timingpower0_t;
+
+typedef struct {
+ ro_bf_t reserved_0_2 : ( 2 - 0 + 1 );
+ ro_bf_t dfi_init_complete : ( 3 - 3 + 1 );
+ ro_bf_t reserved_4_13 : ( 13 - 4 + 1 );
+ ro_bf_t training_complete : ( 14 - 14 + 1 );
+ ro_bf_t reserved_15_30 : ( 30 - 15 + 1 );
+ rw_bf_t timing_set_sw : ( 31 - 31 + 1 );
+} drex_phystatus_t;
+
+typedef struct {
+ ro_bf_t reserved_0_3 : ( 3 - 0 + 1 );
+ rw_bf_t t_src : ( 7 - 4 + 1 );
+ rw_bf_t t_srr : ( 9 - 8 + 1 );
+ ro_bf_t reserved_10_11 : ( 11 - 10 + 1 );
+ rw_bf_t t_mrr : ( 13 - 12 + 1 );
+ ro_bf_t reserved_14_31 : ( 31 - 14 + 1 );
+} drex_etctiming_t;
+
+typedef struct {
+ ro_bf_t chip_busy_state : ( 3 - 0 + 1 );
+ ro_bf_t chip_pd_state : ( 7 - 4 + 1 );
+ ro_bf_t chip_sref_state : ( 11 - 8 + 1 );
+ ro_bf_t reserved_12_31 : ( 31 - 12 + 1 );
+} drex_chipstatus_t;
+
+typedef struct {
+ rw_bf_t rd_fetch : ( 2 - 0 + 1 );
+ ro_bf_t reserved_3 : ( 3 - 3 + 1 );
+ rw_bf_t vref_setting : ( 11 - 4 + 1 );
+ ro_bf_t reserved_12_31 : ( 31 - 12 + 1 );
+} drex_rdfetch0_t;
+
+typedef struct {
+ rw_bf_t rd_fetch : ( 2 - 0 + 1 );
+ ro_bf_t reserved_3 : ( 3 - 3 + 1 );
+ rw_bf_t vref_setting : ( 11 - 4 + 1 );
+ ro_bf_t reserved_12_31 : ( 31 - 12 + 1 );
+} drex_rdfetch1_t;
+
+typedef struct {
+ ro_bf_t mr_status : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} drex_mrstatus_t;
+
+typedef struct {
+ ro_bf_t reserved_0 : ( 0 - 0 + 1 );
+ rw_bf_t phy_wrcsgap_en : ( 1 - 1 + 1 );
+ rw_bf_t ca_odt_en : ( 3 - 2 + 1 );
+ rw_bf_t ca_stable : ( 4 - 4 + 1 );
+ rw_bf_t vrcg_reset : ( 5 - 5 + 1 );
+ rw_bf_t fsp_wr : ( 6 - 6 + 1 );
+ rw_bf_t fsp_op : ( 7 - 7 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} drex_etccontrol0_t;
+
+typedef struct {
+ ro_bf_t reserved_0 : ( 0 - 0 + 1 );
+ rw_bf_t phy_wrcsgap_en : ( 1 - 1 + 1 );
+ rw_bf_t ca_odt_en : ( 3 - 2 + 1 );
+ rw_bf_t ca_stable : ( 4 - 4 + 1 );
+ rw_bf_t vrcg_reset : ( 5 - 5 + 1 );
+ rw_bf_t fsb_wr : ( 6 - 6 + 1 );
+ rw_bf_t fsp_op : ( 7 - 7 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} drex_etccontrol1_t;
+
+typedef struct {
+ rw_bf_t cfg_qos : ( 11 - 0 + 1 );
+ ro_bf_t rsvd1 : ( 15 - 12 + 1 );
+ rw_bf_t cfg_qos_th : ( 27 - 16 + 1 );
+ ro_bf_t reserved_28_31 : ( 31 - 28 + 1 );
+} drex_qoscontrol_t;
+
+typedef struct {
+ drex_qoscontrol_t qos;
+ ro_bf_t reserved;
+}drex_qoscontroln_t;
+
+typedef struct {
+ rw_bf_t timing_set_sw_con : ( 0 - 0 + 1 );
+ ro_bf_t reserved_1_3 : ( 3 - 1 + 1 );
+ rw_bf_t timing_set_sw : ( 4 - 4 + 1 );
+ ro_bf_t reserved_5_31 : ( 31 - 5 + 1 );
+} drex_timingsetsw_t;
+
+typedef struct {
+ rw_bf_t t_ras : ( 5 - 0 + 1 );
+ rw_bf_t t_rc : ( 11 - 6 + 1 );
+ rw_bf_t t_rcd : ( 15 - 12 + 1 );
+ rw_bf_t t_rp : ( 19 - 16 + 1 );
+ rw_bf_t t_rrd : ( 23 - 20 + 1 );
+ rw_bf_t t_rfc : ( 31 - 24 + 1 );
+} drex_timingrow1_t;
+
+typedef struct {
+ rw_bf_t rl : ( 5 - 0 + 1 );
+ rw_bf_t dqsck : ( 9 - 6 + 1 );
+ rw_bf_t wl : ( 13 - 10 + 1 );
+ rw_bf_t t_r2r_c2c : ( 15 - 14 + 1 );
+ rw_bf_t t_w2w_c2c : ( 18 - 16 + 1 );
+ rw_bf_t t_to_w_5th : ( 19 - 19 + 1 );
+ rw_bf_t t_rtp : ( 23 - 20 + 1 );
+ rw_bf_t t_wr : ( 27 - 24 + 1 );
+ rw_bf_t t_wtr : ( 31 - 28 + 1 );
+} drex_timingdata1_t;
+
+typedef struct {
+ rw_bf_t t_mrd : ( 3 - 0 + 1 );
+ rw_bf_t t_cke : ( 7 - 4 + 1 );
+ rw_bf_t t_xp : ( 15 - 8 + 1 );
+ rw_bf_t t_xsr : ( 25 - 16 + 1 );
+ rw_bf_t t_faw : ( 31 - 26 + 1 );
+} drex_timingpower1_t;
+
+typedef struct {
+ rw_bf_t brb_rsv_en_r0 : ( 0 - 0 + 1 );
+ rw_bf_t brb_rsv_en_r1 : ( 1 - 1 + 1 );
+ rw_bf_t brb_rsv_en_r2 : ( 2 - 2 + 1 );
+ rw_bf_t brb_rsv_en_r3 : ( 3 - 3 + 1 );
+ rw_bf_t brb_rsv_en_w0 : ( 4 - 4 + 1 );
+ rw_bf_t brb_rsv_en_w1 : ( 5 - 5 + 1 );
+ rw_bf_t brb_rsv_en_w2 : ( 6 - 6 + 1 );
+ rw_bf_t brb_rsv_en_w3 : ( 7 - 7 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} drex_brbrsvcontrol_t;
+
+typedef struct {
+ rw_bf_t brb_rsv_th_r0 : ( 3 - 0 + 1 );
+ rw_bf_t brb_rsv_th_r1 : ( 7 - 4 + 1 );
+ rw_bf_t brb_rsv_th_r2 : ( 11 - 8 + 1 );
+ rw_bf_t brb_rsv_th_r3 : ( 15 - 12 + 1 );
+ rw_bf_t brb_rsv_th_w0 : ( 19 - 16 + 1 );
+ rw_bf_t brb_rsv_th_w1 : ( 23 - 20 + 1 );
+ rw_bf_t brb_rsv_th_w2 : ( 27 - 24 + 1 );
+ rw_bf_t brb_rsv_th_w3 : ( 31 - 28 + 1 );
+} drex_brbrsvconfig_t;
+
+typedef struct {
+ rw_bf_t brb_qos_timer_dec : ( 11 - 0 + 1 );
+ ro_bf_t reserved_12_31 : ( 31 - 12 + 1 );
+} drex_brbqosconfig_t;
+
+typedef struct {
+ rw_bf_t data_rsv_en_r0 : ( 0 - 0 + 1 );
+ rw_bf_t data_rsv_en_r1 : ( 1 - 1 + 1 );
+ rw_bf_t data_rsv_en_r2 : ( 2 - 2 + 1 );
+ rw_bf_t data_rsv_en_r3 : ( 3 - 3 + 1 );
+ rw_bf_t data_rsv_en_w0 : ( 4 - 4 + 1 );
+ rw_bf_t data_rsv_en_w1 : ( 5 - 5 + 1 );
+ rw_bf_t data_rsv_en_w2 : ( 6 - 6 + 1 );
+ rw_bf_t data_rsv_en_w3 : ( 7 - 7 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} drex_datarsvcontrol_t;
+
+typedef struct {
+ rw_bf_t data_rsv_th_r0 : ( 7 - 0 + 1 );
+ rw_bf_t data_rsv_th_r1 : ( 15 - 8 + 1 );
+ rw_bf_t data_rsv_th_r2 : ( 23 - 16 + 1 );
+ rw_bf_t data_rsv_th_r3 : ( 31 - 24 + 1 );
+} drex_rdatarsvconfig_t;
+
+typedef struct {
+ rw_bf_t data_rsv_th_w0 : ( 7 - 0 + 1 );
+ rw_bf_t data_rsv_th_w1 : ( 15 - 8 + 1 );
+ rw_bf_t data_rsv_th_w2 : ( 23 - 16 + 1 );
+ rw_bf_t data_rsv_th_w3 : ( 31 - 24 + 1 );
+} drex_wdatarsvconfig_t;
+
+typedef struct {
+ ro_bf_t reserved_0_3 : ( 3 - 0 + 1 );
+ rw_bf_t t_wlo : ( 7 - 4 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} drex_wrlvlconfig0_t;
+
+typedef struct {
+ rw_bf_t wrlvl_wrdata_en : ( 0 - 0 + 1 );
+ ro_bf_t reserved_1_31 : ( 31 - 1 + 1 );
+} drex_wrlvlconfig1_t;
+
+typedef struct {
+ ro_bf_t wrlvl_fsm : ( 4 - 0 + 1 );
+ ro_bf_t reserved_5_31 : ( 31 - 5 + 1 );
+} drex_wrlvlstatus_t;
+
+typedef struct {
+ rw_bf_t perev_clk_en : ( 0 - 0 + 1 );
+ ro_bf_t reserved_1_31 : ( 31 - 1 + 1 );
+} drex_ppcclkcon_t;
+
+typedef struct {
+ rw_bf_t perev0_sel : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} drex_perevconfig0_t;
+
+typedef struct {
+ rw_bf_t perev1_sel : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} drex_perevconfig1_t;
+
+typedef struct {
+ rw_bf_t perev2_sel : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} drex_perevconfig2_t;
+
+typedef struct {
+ rw_bf_t perev3_sel : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} drex_perevconfig3_t;
+
+typedef struct {
+ ro_bf_t ctrl_io_rdata : ( 31 - 0 + 1 );
+} drex_ctrl_io_rdata_t;
+
+typedef struct {
+ ro_bf_t reserved_0 : ( 0 - 0 + 1 );
+ rw_bf_t emergent_r_config : ( 31 - 1 + 1 );
+} drex_emergent_config0_t;
+
+typedef struct {
+ ro_bf_t reserved_0 : ( 0 - 0 + 1 );
+ rw_bf_t emergent_w_config : ( 31 - 1 + 1 );
+} drex_emergent_config1_t;
+
+typedef struct {
+ rw_bf_t bp_en : ( 0 - 0 + 1 );
+ rw_bf_t bp_under_emergent : ( 1 - 1 + 1 );
+ ro_bf_t reserved_2_31 : ( 31 - 2 + 1 );
+} drex_bp_control_t;
+
+typedef struct {
+ rw_bf_t bp_on_th_brb : ( 2 - 0 + 1 );
+ ro_bf_t reserved_3_7 : ( 7 - 3 + 1 );
+ rw_bf_t bp_off_th_brb : ( 10 - 8 + 1 );
+ ro_bf_t reserved_11_15 : ( 15 - 11 + 1 );
+ rw_bf_t bp_on_th_data : ( 21 - 16 + 1 );
+ ro_bf_t reserved_22_23 : ( 23 - 22 + 1 );
+ rw_bf_t bp_off_th_data : ( 29 - 24 + 1 );
+ ro_bf_t reserved_30_31 : ( 31 - 30 + 1 );
+} drex_bp_config_r_t;
+
+typedef struct {
+ rw_bf_t bp_on_th_brb : ( 2 - 0 + 1 );
+ ro_bf_t reserved_3_7 : ( 7 - 3 + 1 );
+ rw_bf_t bp_off_th_brb : ( 10 - 8 + 1 );
+ ro_bf_t reserved_11_15 : ( 15 - 11 + 1 );
+ rw_bf_t bp_on_th_data : ( 21 - 16 + 1 );
+ ro_bf_t reserved_22_23 : ( 23 - 22 + 1 );
+ rw_bf_t bp_off_th_data : ( 29 - 24 + 1 );
+ ro_bf_t reserved_30_31 : ( 31 - 30 + 1 );
+} drex_bp_config_w_t;
+
+typedef struct {
+ drex_bp_control_t BP_CONTROL;
+ drex_bp_config_r_t BP_CONFIG_R;
+ drex_bp_config_w_t BP_CONFIG_W;
+ ro_bf_t reserved;
+}drex_bp_control_set_t;
+
+typedef struct {
+ rw_bf_t diable_fifo_emergent : ( 3 - 0 + 1 );
+ ro_bf_t reserved_4_31 : ( 31 - 4 + 1 );
+} drex_fifo_emer_config_t;
+
+typedef struct {
+ rw_bf_t ca_pipeline : ( 1 - 0 + 1 );
+ ro_bf_t reserved_2_3 : ( 3 - 2 + 1 );
+ rw_bf_t dq_pipeline : ( 6 - 4 + 1 );
+ ro_bf_t reserved_7_31 : ( 31 - 7 + 1 );
+} drex_pl_config_t;
+
+typedef struct {
+ rw_bf_t all_init_done : ( 0 - 0 + 1 );
+ ro_bf_t reserved_1_31 : ( 31 - 1 + 1 );
+} drex_all_int_indi_t;
+
+typedef struct {
+ rw_bf_t t_rdlvl_en : ( 3 - 0 + 1 );
+ rw_bf_t t_rdlvl_rr : ( 8 - 4 + 1 );
+ ro_bf_t reserved_9_11 : ( 11 - 9 + 1 );
+ rw_bf_t t_wrtrn_en : ( 15 - 12 + 1 );
+ rw_bf_t t_wrtrn_wr : ( 19 - 16 + 1 );
+ rw_bf_t t_wrtrn_rw : ( 24 - 20 + 1 );
+ ro_bf_t reserved_25_27 : ( 27 - 25 + 1 );
+ rw_bf_t t_rdtrd : ( 31 - 28 + 1 );
+} drex_train_timing0_t;
+
+typedef struct {
+ rw_bf_t t_rdlvl_en : ( 3 - 0 + 1 );
+ rw_bf_t t_rdlvl_rr : ( 8 - 4 + 1 );
+ ro_bf_t reserved_9_11 : ( 11 - 9 + 1 );
+ rw_bf_t t_wrtrn_en : ( 15 - 12 + 1 );
+ rw_bf_t t_wrtrn_wr : ( 19 - 16 + 1 );
+ rw_bf_t t_wrtrn_rw : ( 24 - 20 + 1 );
+ ro_bf_t reserved_25_27 : ( 27 - 25 + 1 );
+ rw_bf_t t_rdtrd : ( 31 - 28 + 1 );
+} drex_train_timing1_t;
+
+typedef struct {
+ rw_bf_t t_ptrain_period : ( 23 - 0 + 1 );
+ ro_bf_t reserved_24_31 : ( 31 - 24 + 1 );
+} drex_hw_ptrain_period0_t;
+
+typedef struct {
+ rw_bf_t t_ptrain_period : ( 23 - 0 + 1 );
+ ro_bf_t reserved_24_31 : ( 31 - 24 + 1 );
+} drex_hw_ptrain_period1_t;
+
+typedef struct {
+ rw_bf_t init_gate_train_chip0 : ( 0 - 0 + 1 );
+ rw_bf_t init_read_train_chip0 : ( 1 - 1 + 1 );
+ rw_bf_t init_write_train_chip0 : ( 2 - 2 + 1 );
+ ro_bf_t reserved_3_15 : ( 15 - 3 + 1 );
+ rw_bf_t init_gate_train_chip1 : ( 16 - 16 + 1 );
+ ro_bf_t reserved_17 : ( 17 - 17 + 1 );
+ rw_bf_t init_write_train_chip1 : ( 18 - 18 + 1 );
+ ro_bf_t reserved_19_31 : ( 31 - 19 + 1 );
+} drex_inittrainconfig_t;
+
+typedef struct {
+ rw_bf_t init_train_start : ( 0 - 0 + 1 );
+ ro_bf_t reserved_1_31 : ( 31 - 1 + 1 );
+} drex_inittraincontrol_t;
+
+typedef struct {
+ rw_bf_t swp_gate_train : ( 0 - 0 + 1 );
+ rw_bf_t swp_read_train : ( 1 - 1 + 1 );
+ rw_bf_t swp_write_train : ( 2 - 2 + 1 );
+ ro_bf_t reserved_3_15 : ( 15 - 3 + 1 );
+ rw_bf_t gate_all_rank : ( 16 - 16 + 1 );
+ ro_bf_t reserved_17 : ( 17 - 17 + 1 );
+ rw_bf_t write_all_rank : ( 18 - 18 + 1 );
+ ro_bf_t reserved_19_31 : ( 31 - 19 + 1 );
+} drex_swptrainconfig_t;
+
+typedef struct {
+ rw_bf_t swp_train_start : ( 0 - 0 + 1 );
+ ro_bf_t reserved_1_31 : ( 31 - 1 + 1 );
+} drex_swptraincontrol_t;
+
+typedef struct {
+ rw_bf_t retrain_gate : ( 0 - 0 + 1 );
+ rw_bf_t retrain_read : ( 1 - 1 + 1 );
+ rw_bf_t retrain_write : ( 2 - 2 + 1 );
+ ro_bf_t reserved_3_7 : ( 7 - 3 + 1 );
+ rw_bf_t periodic_gate : ( 8 - 8 + 1 );
+ rw_bf_t periodic_read : ( 9 - 9 + 1 );
+ rw_bf_t periodic_write : ( 10 - 10 + 1 );
+ ro_bf_t reserved_11_15 : ( 15 - 11 + 1 );
+ rw_bf_t retrain_gate_all_rank : ( 16 - 16 + 1 );
+ ro_bf_t reserved_17 : ( 17 - 17 + 1 );
+ rw_bf_t retrain_write_all_rank : ( 18 - 18 + 1 );
+ ro_bf_t reserved_19_23 : ( 23 - 19 + 1 );
+ rw_bf_t periodic_gate_all_rank : ( 24 - 24 + 1 );
+ ro_bf_t reserved_25 : ( 25 - 25 + 1 );
+ rw_bf_t periodic_write_all_rank : ( 26 - 26 + 1 );
+ ro_bf_t reserved_27_31 : ( 31 - 27 + 1 );
+} drex_hwptrainconfig0_t;
+
+typedef struct {
+ rw_bf_t retrain_gate : ( 0 - 0 + 1 );
+ rw_bf_t retrain_read : ( 1 - 1 + 1 );
+ rw_bf_t retrain_write : ( 2 - 2 + 1 );
+ ro_bf_t reserved_3_7 : ( 7 - 3 + 1 );
+ rw_bf_t periodic_gate : ( 8 - 8 + 1 );
+ rw_bf_t periodic_read : ( 9 - 9 + 1 );
+ rw_bf_t periodic_write : ( 10 - 10 + 1 );
+ ro_bf_t reserved_11_15 : ( 15 - 11 + 1 );
+ rw_bf_t retrain_gate_all_rank : ( 16 - 16 + 1 );
+ ro_bf_t reserved_17 : ( 17 - 17 + 1 );
+ rw_bf_t retrain_write_all_rank : ( 18 - 18 + 1 );
+ ro_bf_t reserved_19_23 : ( 23 - 19 + 1 );
+ rw_bf_t periodic_gate_all_rank : ( 24 - 24 + 1 );
+ ro_bf_t reserved_25 : ( 25 - 25 + 1 );
+ rw_bf_t periodic_write_all_rank : ( 26 - 26 + 1 );
+ ro_bf_t reserved_27_31 : ( 31 - 27 + 1 );
+} drex_hwptrainconfig1_t;
+
+typedef struct {
+ rw_bf_t retrain_en : ( 0 - 0 + 1 );
+ rw_bf_t hw_periodic_train_en : ( 1 - 1 + 1 );
+ ro_bf_t reserved_2_31 : ( 31 - 2 + 1 );
+} drex_hwptraincontrol0_t;
+
+typedef struct {
+ rw_bf_t retrain_en : ( 0 - 0 + 1 );
+ rw_bf_t hw_periodic_train_en : ( 1 - 1 + 1 );
+ ro_bf_t reserved_2_31 : ( 31 - 2 + 1 );
+} drex_hwptraincontrol1_t;
+
+typedef struct {
+ rw_bf_t wrtra_wrdata_p1 : ( 15 - 0 + 1 );
+ rw_bf_t wrtra_wrdata_p0 : ( 31 - 16 + 1 );
+} drex_wrtra_pattern0_t;
+
+typedef struct {
+ rw_bf_t wrtra_wrdata_p3 : ( 15 - 0 + 1 );
+ rw_bf_t wrtra_wrdata_p2 : ( 31 - 16 + 1 );
+} drex_wrtra_pattern1_t;
+
+typedef struct {
+ rw_bf_t wrtra_wrdata_dm_p3 : ( 1 - 0 + 1 );
+ rw_bf_t wrtra_wrdata_dm_p2 : ( 3 - 2 + 1 );
+ rw_bf_t wrtra_wrdata_dm_p1 : ( 5 - 4 + 1 );
+ rw_bf_t wrtra_wrdata_dm_p0 : ( 7 - 6 + 1 );
+ rw_bf_t rsvd : ( 31 - 8 + 1 );
+} drex_wrtra_pattern2_t;
+
+typedef struct {
+ ro_bf_t csysreq : ( 0 - 0 + 1 );
+ ro_bf_t csysack : ( 1 - 1 + 1 );
+ ro_bf_t reserved_2_3 : ( 3 - 2 + 1 );
+ ro_bf_t lpi_state : ( 6 - 4 + 1 );
+ ro_bf_t reserved_7 : ( 7 - 7 + 1 );
+ ro_bf_t agent_axl_state : ( 14 - 8 + 1 );
+ ro_bf_t reserved_15 : ( 15 - 15 + 1 );
+ ro_bf_t pause_req : ( 16 - 16 + 1 );
+ ro_bf_t pause_ack : ( 17 - 17 + 1 );
+ ro_bf_t reserved_18_19 : ( 19 - 18 + 1 );
+ ro_bf_t pause_state : ( 22 - 20 + 1 );
+ ro_bf_t reserved_23_31 : ( 31 - 23 + 1 );
+} drex_lpi_pause_state_t;
+
+typedef struct {
+ ro_bf_t fifo_empty_ar : ( 3 - 0 + 1 );
+ ro_bf_t fifo_empty_aw : ( 7 - 4 + 1 );
+ ro_bf_t brb_empty_rd : ( 8 - 8 + 1 );
+ ro_bf_t brb_empty_wr : ( 9 - 9 + 1 );
+ ro_bf_t fifo_empty_bresp : ( 14 - 10 + 1 );
+ ro_bf_t reserved_15_31 : ( 31 - 15 + 1 );
+} drex_empty_state_t;
+
+typedef struct {
+ ro_bf_t occupancy_p0 : ( 7 - 0 + 1 );
+ ro_bf_t occupancy_p1 : ( 15 - 8 + 1 );
+ ro_bf_t occupancy_p2 : ( 23 - 16 + 1 );
+ ro_bf_t occupancy_p3 : ( 31 - 24 + 1 );
+} drex_rbuf_occupancy_t;
+
+typedef struct {
+ ro_bf_t occupancy_p0 : ( 7 - 0 + 1 );
+ ro_bf_t occupancy_p1 : ( 15 - 8 + 1 );
+ ro_bf_t occupancy_p2 : ( 23 - 16 + 1 );
+ ro_bf_t occupancy_p3 : ( 31 - 24 + 1 );
+} drex_wbuf_occupancy_t;
+
+typedef struct {
+ ro_bf_t reserved_0 : ( 0 - 0 + 1 );
+ ro_bf_t emergent : ( 31 - 1 + 1 );
+} drex_emergent_r_t;
+
+typedef struct {
+ ro_bf_t reserved_0 : ( 0 - 0 + 1 );
+ ro_bf_t emergent : ( 31 - 1 + 1 );
+} drex_emergent_w_t;
+
+typedef struct {
+ ro_bf_t backpressure_r : ( 3 - 0 + 1 );
+ ro_bf_t backpressure_w : ( 7 - 4 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} drex_backpressure_t;
+
+typedef struct {
+ ro_bf_t fifo_p0 : ( 3 - 0 + 1 );
+ ro_bf_t fifo_p1 : ( 7 - 4 + 1 );
+ ro_bf_t fifo_p2 : ( 11 - 8 + 1 );
+ ro_bf_t fifo_p3 : ( 15 - 12 + 1 );
+ ro_bf_t reserved_16_31 : ( 31 - 16 + 1 );
+} drex_rfifo_valid_state_t;
+
+typedef struct {
+ ro_bf_t fifo_p0 : ( 3 - 0 + 1 );
+ ro_bf_t fifo_p1 : ( 7 - 4 + 1 );
+ ro_bf_t fifo_p2 : ( 11 - 8 + 1 );
+ ro_bf_t fifo_p3 : ( 15 - 12 + 1 );
+ ro_bf_t reserved_16_31 : ( 31 - 16 + 1 );
+} drex_wfifo_valid_state_t;
+
+typedef struct {
+ ro_bf_t fifo_p0 : ( 3 - 0 + 1 );
+ ro_bf_t fifo_p1 : ( 7 - 4 + 1 );
+ ro_bf_t fifo_p2 : ( 11 - 8 + 1 );
+ ro_bf_t fifo_p3 : ( 15 - 12 + 1 );
+ ro_bf_t reserved_16_31 : ( 31 - 16 + 1 );
+} drex_cfifo_valid_state_t;
+
+typedef struct {
+ rw_bf_t r_brb : ( 31 - 0 + 1 );
+} drex_r_brb_valid_state_t;
+
+typedef struct {
+ rw_bf_t w_brb : ( 31 - 0 + 1 );
+} drex_w_brb_valid_state_t;
+
+typedef struct {
+ rw_bf_t axmarker_or_axid : ( 15 - 0 + 1 );
+ ro_bf_t reserved_16_31 : ( 31 - 16 + 1 );
+} drex_info_config_t;
+
+typedef struct {
+ ro_bf_t fifo_brb0_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb0_1 : ( 31 - 16 + 1 );
+} drex_r_fifo_info_p0_0_t;
+
+typedef struct {
+ ro_bf_t fifo_brb1_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb1_1 : ( 31 - 16 + 1 );
+} drex_r_fifo_info_p0_1_t;
+
+typedef struct {
+ ro_bf_t fifo_brb0_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb0_1 : ( 31 - 16 + 1 );
+} drex_r_fifo_info_p1_0_t;
+
+typedef struct {
+ ro_bf_t fifo_brb1_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb1_1 : ( 31 - 16 + 1 );
+} drex_r_fifo_info_p1_1_t;
+
+typedef struct {
+ ro_bf_t fifo_brb0_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb0_1 : ( 31 - 16 + 1 );
+} drex_r_fifo_info_p2_0_t;
+
+typedef struct {
+ ro_bf_t fifo_brb1_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb1_1 : ( 31 - 16 + 1 );
+} drex_r_fifo_info_p2_1_t;
+
+typedef struct {
+ ro_bf_t fifo_brb0_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb0_1 : ( 31 - 16 + 1 );
+} drex_r_fifo_info_p3_0_t;
+
+typedef struct {
+ ro_bf_t fifo_brb1_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb1_1 : ( 31 - 16 + 1 );
+} drex_r_fifo_info_p3_1_t;
+
+typedef struct {
+ ro_bf_t fifo_brb0_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb0_1 : ( 31 - 16 + 1 );
+} drex_w_fifo_info_p0_0_t;
+
+typedef struct {
+ ro_bf_t fifo_brb1_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb1_1 : ( 31 - 16 + 1 );
+} drex_w_fifo_info_p0_1_t;
+
+typedef struct {
+ ro_bf_t fifo_brb0_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb0_1 : ( 31 - 16 + 1 );
+} drex_w_fifo_info_p1_0_t;
+
+typedef struct {
+ ro_bf_t fifo_brb1_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb1_1 : ( 31 - 16 + 1 );
+} drex_w_fifo_info_p1_1_t;
+
+typedef struct {
+ ro_bf_t fifo_brb0_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb0_1 : ( 31 - 16 + 1 );
+} drex_w_fifo_info_p2_0_t;
+
+typedef struct {
+ ro_bf_t fifo_brb1_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb1_1 : ( 31 - 16 + 1 );
+} drex_w_fifo_info_p2_1_t;
+
+typedef struct {
+ ro_bf_t fifo_brb0_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb0_1 : ( 31 - 16 + 1 );
+} drex_w_fifo_info_p3_0_t;
+
+typedef struct {
+ ro_bf_t fifo_brb1_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb1_1 : ( 31 - 16 + 1 );
+} drex_w_fifo_info_p3_1_t;
+
+typedef struct {
+ ro_bf_t fifo_brb1_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb1_1 : ( 31 - 16 + 1 );
+} drex_c_fifo_info_p0_t;
+
+typedef struct {
+ ro_bf_t fifo_brb1_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb1_1 : ( 31 - 16 + 1 );
+} drex_c_fifo_info_p1_t;
+
+typedef struct {
+ ro_bf_t fifo_brb1_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb1_1 : ( 31 - 16 + 1 );
+} drex_c_fifo_info_p2_t;
+
+typedef struct {
+ ro_bf_t fifo_brb1_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb1_1 : ( 31 - 16 + 1 );
+} drex_c_fifo_info_p3_t;
+
+typedef struct {
+ ro_bf_t r_brb0_0 : ( 15 - 0 + 1 );
+ ro_bf_t r_brb0_1 : ( 31 - 16 + 1 );
+} drex_r_brb0_1_0_axid_t;
+
+typedef struct {
+ ro_bf_t r_brb0_2 : ( 15 - 0 + 1 );
+ ro_bf_t r_brb0_3 : ( 31 - 16 + 1 );
+} drex_r_brb0_3_2_axid_t;
+
+typedef struct {
+ ro_bf_t r_brb0_4 : ( 15 - 0 + 1 );
+ ro_bf_t r_brb0_5 : ( 31 - 16 + 1 );
+} drex_r_brb0_5_4_axid_t;
+
+typedef struct {
+ ro_bf_t r_brb0_6 : ( 15 - 0 + 1 );
+ ro_bf_t r_brb0_7 : ( 31 - 16 + 1 );
+} drex_r_brb0_7_6_axid_t;
+
+typedef struct {
+ ro_bf_t r_brb1_0 : ( 15 - 0 + 1 );
+ ro_bf_t r_brb1_1 : ( 31 - 16 + 1 );
+} drex_r_brb1_1_0_axid_t;
+
+typedef struct {
+ ro_bf_t r_brb1_2 : ( 15 - 0 + 1 );
+ ro_bf_t r_brb1_3 : ( 31 - 16 + 1 );
+} drex_r_brb1_3_2_axid_t;
+
+typedef struct {
+ ro_bf_t r_brb1_4 : ( 15 - 0 + 1 );
+ ro_bf_t r_brb1_5 : ( 31 - 16 + 1 );
+} drex_r_brb1_5_4_axid_t;
+
+typedef struct {
+ ro_bf_t r_brb1_6 : ( 15 - 0 + 1 );
+ ro_bf_t r_brb1_7 : ( 31 - 16 + 1 );
+} drex_r_brb1_7_6_axid_t;
+
+typedef struct {
+ ro_bf_t w_brb0_0 : ( 15 - 0 + 1 );
+ ro_bf_t w_brb0_1 : ( 31 - 16 + 1 );
+} drex_w_brb0_1_0_axid_t;
+
+typedef struct {
+ ro_bf_t w_brb0_2 : ( 15 - 0 + 1 );
+ ro_bf_t w_brb0_3 : ( 31 - 16 + 1 );
+} drex_w_brb0_3_2_axid_t;
+
+typedef struct {
+ ro_bf_t w_brb0_4 : ( 15 - 0 + 1 );
+ ro_bf_t w_brb0_5 : ( 31 - 16 + 1 );
+} drex_w_brb0_5_4_axid_t;
+
+typedef struct {
+ ro_bf_t w_brb0_6 : ( 15 - 0 + 1 );
+ ro_bf_t w_brb0_7 : ( 31 - 16 + 1 );
+} drex_w_brb0_7_6_axid_t;
+
+typedef struct {
+ ro_bf_t w_brb1_0 : ( 15 - 0 + 1 );
+ ro_bf_t w_brb1_1 : ( 31 - 16 + 1 );
+} drex_w_brb1_1_0_axid_t;
+
+typedef struct {
+ ro_bf_t w_brb1_2 : ( 15 - 0 + 1 );
+ ro_bf_t w_brb1_3 : ( 31 - 16 + 1 );
+} drex_w_brb1_3_2_axid_t;
+
+typedef struct {
+ ro_bf_t w_brb1_4 : ( 15 - 0 + 1 );
+ ro_bf_t w_brb1_5 : ( 31 - 16 + 1 );
+} drex_w_brb1_5_4_axid_t;
+
+typedef struct {
+ ro_bf_t w_brb1_6 : ( 15 - 0 + 1 );
+ ro_bf_t w_brb1_7 : ( 31 - 16 + 1 );
+} drex_w_brb1_7_6_axid_t;
+
+typedef struct {
+ ro_bf_t phy_upd_req : ( 0 - 0 + 1 );
+ ro_bf_t phy_upd_ack : ( 1 - 1 + 1 );
+ ro_bf_t reserved_2_31 : ( 31 - 2 + 1 );
+} drex_phy_upd_state_t;
+
+typedef struct {
+ ro_bf_t dfi_rdlvl_gate_en : ( 0 - 0 + 1 );
+ ro_bf_t dfi_rdlvl_en : ( 1 - 1 + 1 );
+ ro_bf_t dfi_rdlvl_wr_en : ( 2 - 2 + 1 );
+ ro_bf_t dfi_lvl_periodic : ( 3 - 3 + 1 );
+ ro_bf_t dfi_train_csn : ( 5 - 4 + 1 );
+ ro_bf_t reserved_6_7 : ( 7 - 6 + 1 );
+ ro_bf_t train_state : ( 16 - 8 + 1 );
+ ro_bf_t reserved_17_31 : ( 31 - 17 + 1 );
+} drex_train_state_t;
+
+typedef struct {
+ rw_bf_t ppc_enable : ( 0 - 0 + 1 );
+ rw_bf_t ppc_counter_reset : ( 1 - 1 + 1 );
+ rw_bf_t cc_reset : ( 2 - 2 + 1 );
+ rw_bf_t cc_divider : ( 3 - 3 + 1 );
+ ro_bf_t rsvd1 : ( 15 - 4 + 1 );
+ rw_bf_t start_mode : ( 16 - 16 + 1 );
+ ro_bf_t reserved_17_31 : ( 31 - 17 + 1 );
+} drex_pmnc_ppc_t;
+
+typedef struct {
+ rw_bf_t pmcnt0 : ( 0 - 0 + 1 );
+ rw_bf_t pmcnt1 : ( 1 - 1 + 1 );
+ rw_bf_t pmcnt2 : ( 2 - 2 + 1 );
+ rw_bf_t pmcnt3 : ( 3 - 3 + 1 );
+ ro_bf_t reserved_4_30 : ( 30 - 4 + 1 );
+ rw_bf_t ccnt : ( 31 - 31 + 1 );
+} drex_cntens_ppc_t;
+
+typedef struct {
+ rw_bf_t pmcnt0 : ( 0 - 0 + 1 );
+ rw_bf_t pmcnt1 : ( 1 - 1 + 1 );
+ rw_bf_t pmcnt2 : ( 2 - 2 + 1 );
+ rw_bf_t pmcnt3 : ( 3 - 3 + 1 );
+ ro_bf_t reserved_4_30 : ( 30 - 4 + 1 );
+ rw_bf_t ccnt : ( 31 - 31 + 1 );
+} drex_cntenc_ppc_t;
+
+typedef struct {
+ rw_bf_t pmcnt0 : ( 0 - 0 + 1 );
+ rw_bf_t pmcnt1 : ( 1 - 1 + 1 );
+ rw_bf_t pmcnt2 : ( 2 - 2 + 1 );
+ rw_bf_t pmcnt3 : ( 3 - 3 + 1 );
+ ro_bf_t reserved_4_30 : ( 30 - 4 + 1 );
+ rw_bf_t ccnt : ( 31 - 31 + 1 );
+} drex_intens_ppc_t;
+
+typedef struct {
+ rw_bf_t pmcnt0 : ( 0 - 0 + 1 );
+ rw_bf_t pmcnt1 : ( 1 - 1 + 1 );
+ rw_bf_t pmcnt2 : ( 2 - 2 + 1 );
+ rw_bf_t pmcnt3 : ( 3 - 3 + 1 );
+ ro_bf_t reserved_4_30 : ( 30 - 4 + 1 );
+ rw_bf_t ccnt : ( 31 - 31 + 1 );
+} drex_intenc_ppc_t;
+
+typedef struct {
+ rw_bf_t pmcnt0 : ( 0 - 0 + 1 );
+ rw_bf_t pmcnt1 : ( 1 - 1 + 1 );
+ rw_bf_t pmcnt2 : ( 2 - 2 + 1 );
+ rw_bf_t pmcnt3 : ( 3 - 3 + 1 );
+ ro_bf_t reserved_4_30 : ( 30 - 4 + 1 );
+ rw_bf_t ccnt : ( 31 - 31 + 1 );
+} drex_flag_ppc_t;
+
+typedef struct {
+ rw_bf_t ccnt : ( 31 - 0 + 1 );
+} drex_ccnt_ppc_t;
+
+typedef struct {
+ rw_bf_t pmcnt : ( 31 - 0 + 1 );
+} drex_pmcnt0_ppc_t;
+
+typedef struct {
+ rw_bf_t pmcnt : ( 31 - 0 + 1 );
+} drex_pmcnt1_ppc_t;
+
+typedef struct {
+ rw_bf_t pmcnt : ( 31 - 0 + 1 );
+} drex_pmcnt2_ppc_t;
+
+typedef struct {
+ rw_bf_t pmcnt : ( 31 - 0 + 1 );
+} drex_pmcnt3_ppc_t;
+
+
+typedef struct {
+ drex_concontrol_t CONCONTROL;
+ drex_memcontrol_t MEMCONTROL;
+ drex_cgcontrol_t CGCONTROL;
+ ro_bf_t reserved_0xC;
+ drex_directcmd_t DIRECTCMD;
+ drex_prechconfig0_t PRECHCONFIG0;
+ drex_phycontrol0_t PHYCONTROL0;
+ drex_prechconfig1_t PRECHCONFIG1;
+ drex_timingrfcpb_t TIMINGRFCPB;
+ drex_zqtiming_t ZQTIMING;
+ drex_pwrdnconfig_t PWRDNCONFIG;
+ ro_bf_t reserved_0x2C;
+ drex_timingaref_t TIMINGAREF;
+ drex_timingrow0_t TIMINGROW0;
+ drex_timingdata0_t TIMINGDATA0;
+ drex_timingpower0_t TIMINGPOWER0;
+ drex_phystatus_t PHYSTATUS;
+ drex_etctiming_t ETCTIMING;
+ drex_chipstatus_t CHIPSTATUS;
+ drex_rdfetch0_t RDFETCH0;
+ drex_rdfetch1_t RDFETCH1;
+ drex_mrstatus_t MRSTATUS;
+ drex_etccontrol0_t ETCCONTROL0;
+ drex_etccontrol1_t ETCCONTROL1;
+ drex_qoscontroln_t QOSCONTROL[16];
+ drex_timingsetsw_t TIMINGSETSW;
+ drex_timingrow1_t TIMINGROW1;
+ drex_timingdata1_t TIMINGDATA1;
+ drex_timingpower1_t TIMINGPOWER1;
+ ro_bf_t reserved_0xF0_0xFC[4];
+ drex_brbrsvcontrol_t BRBRSVCONTROL;
+ drex_brbrsvconfig_t BRBRSVCONFIG;
+ drex_brbqosconfig_t BRBQOSCONFIG;
+ drex_datarsvcontrol_t DATARSVCONTROL;
+ drex_rdatarsvconfig_t RDATARSVCONFIG;
+ drex_wdatarsvconfig_t WDATARSVCONFIG;
+ ro_bf_t reserved_0x118_0x11C[2];
+ drex_wrlvlconfig0_t WRLVLCONFIG0;
+ drex_wrlvlconfig1_t WRLVLCONFIG1;
+ drex_wrlvlstatus_t WRLVLSTATUS;
+ ro_bf_t reserved_0x12C;
+ drex_ppcclkcon_t PPCCLKCON;
+ drex_perevconfig0_t PEREVCONFIG0;
+ drex_perevconfig1_t PEREVCONFIG1;
+ drex_perevconfig2_t PEREVCONFIG2;
+ drex_perevconfig3_t PEREVCONFIG3;
+ ro_bf_t reserved_0x144_0x14C[3];
+ drex_ctrl_io_rdata_t CTRL_IO_RDATA;
+ ro_bf_t reserved_0x154_0x1FC[43];
+ drex_emergent_config0_t EMERGENT_CONFIG0;
+ drex_emergent_config1_t EMERGENT_CONFIG1;
+ ro_bf_t reserved_0x208_0x20C[2];
+ drex_bp_control_set_t BPCON[4];
+ drex_fifo_emer_config_t FIFO_EMER_CONFIG;
+ ro_bf_t reserved_0x254_0x30C[47];
+ drex_pl_config_t PL_CONFIG;
+ ro_bf_t reserved_0x314_0x3FC[59];
+ drex_all_int_indi_t ALL_INT_INDI;
+ ro_bf_t reserved_0x404_0x40C[3];
+ drex_train_timing0_t TRAIN_TIMING0;
+ drex_train_timing1_t TRAIN_TIMING1;
+ ro_bf_t reserved_0x418_0x41C[2];
+ drex_hw_ptrain_period0_t HW_PTRAIN_PERIOD0;
+ drex_hw_ptrain_period1_t HW_PTRAIN_PERIOD1;
+ ro_bf_t reserved_0x428_0x42C[2];
+ drex_inittrainconfig_t INITTRAINCONFIG;
+ drex_inittraincontrol_t INITTRAINCONTROL;
+ drex_swptrainconfig_t SWPTRAINCONFIG;
+ drex_swptraincontrol_t SWPTRAINCONTROL;
+ drex_hwptrainconfig0_t HWPTRAINCONFIG0;
+ drex_hwptrainconfig1_t HWPTRAINCONFIG1;
+ ro_bf_t reserved_0x448_0x44C[2];
+ drex_hwptraincontrol0_t HWPTRAINCONTROL0;
+ drex_hwptraincontrol1_t HWPTRAINCONTROL1;
+ ro_bf_t reserved_0x458_0x45C[2];
+ drex_wrtra_pattern0_t WRTRA_PATTERN0;
+ drex_wrtra_pattern1_t WRTRA_PATTERN1;
+ drex_wrtra_pattern2_t WRTRA_PATTERN2;
+ ro_bf_t reserved_0x46C_0x4FC[37];
+ drex_lpi_pause_state_t LPI_PAUSE_STATE;
+ drex_empty_state_t EMPTY_STATE;
+ drex_rbuf_occupancy_t RBUF_OCCUPANCY;
+ drex_wbuf_occupancy_t WBUF_OCCUPANCY;
+ drex_emergent_r_t EMERGENT_R;
+ drex_emergent_w_t EMERGENT_W;
+ drex_backpressure_t BACKPRESSURE;
+ drex_rfifo_valid_state_t RFIFO_VALID_STATE;
+ drex_wfifo_valid_state_t WFIFO_VALID_STATE;
+ drex_cfifo_valid_state_t CFIFO_VALID_STATE;
+ drex_r_brb_valid_state_t R_BRB_VALID_STATE;
+ drex_w_brb_valid_state_t W_BRB_VALID_STATE;
+ drex_info_config_t INFO_CONFIG;
+ ro_bf_t reserved_0x534_0x53C[3];
+ drex_r_fifo_info_p0_0_t R_FIFO_INFO_P0_0;
+ drex_r_fifo_info_p0_1_t R_FIFO_INFO_P0_1;
+ drex_r_fifo_info_p1_0_t R_FIFO_INFO_P1_0;
+ drex_r_fifo_info_p1_1_t R_FIFO_INFO_P1_1;
+ drex_r_fifo_info_p2_0_t R_FIFO_INFO_P2_0;
+ drex_r_fifo_info_p2_1_t R_FIFO_INFO_P2_1;
+ drex_r_fifo_info_p3_0_t R_FIFO_INFO_P3_0;
+ drex_r_fifo_info_p3_1_t R_FIFO_INFO_P3_1;
+ drex_w_fifo_info_p0_0_t W_FIFO_INFO_P0_0;
+ drex_w_fifo_info_p0_1_t W_FIFO_INFO_P0_1;
+ drex_w_fifo_info_p1_0_t W_FIFO_INFO_P1_0;
+ drex_w_fifo_info_p1_1_t W_FIFO_INFO_P1_1;
+ drex_w_fifo_info_p2_0_t W_FIFO_INFO_P2_0;
+ drex_w_fifo_info_p2_1_t W_FIFO_INFO_P2_1;
+ drex_w_fifo_info_p3_0_t W_FIFO_INFO_P3_0;
+ drex_w_fifo_info_p3_1_t W_FIFO_INFO_P3_1;
+ drex_c_fifo_info_p0_t C_FIFO_INFO_P0;
+ drex_c_fifo_info_p1_t C_FIFO_INFO_P1;
+ drex_c_fifo_info_p2_t C_FIFO_INFO_P2;
+ drex_c_fifo_info_p3_t C_FIFO_INFO_P3;
+ drex_r_brb0_1_0_axid_t R_BRB0_1_0_AXID;
+ drex_r_brb0_3_2_axid_t R_BRB0_3_2_AXID;
+ drex_r_brb0_5_4_axid_t R_BRB0_5_4_AXID;
+ drex_r_brb0_7_6_axid_t R_BRB0_7_6_AXID;
+ drex_r_brb1_1_0_axid_t R_BRB1_1_0_AXID;
+ drex_r_brb1_3_2_axid_t R_BRB1_3_2_AXID;
+ drex_r_brb1_5_4_axid_t R_BRB1_5_4_AXID;
+ drex_r_brb1_7_6_axid_t R_BRB1_7_6_AXID;
+ drex_w_brb0_1_0_axid_t W_BRB0_1_0_AXID;
+ drex_w_brb0_3_2_axid_t W_BRB0_3_2_AXID;
+ drex_w_brb0_5_4_axid_t W_BRB0_5_4_AXID;
+ drex_w_brb0_7_6_axid_t W_BRB0_7_6_AXID;
+ drex_w_brb1_1_0_axid_t W_BRB1_1_0_AXID;
+ drex_w_brb1_3_2_axid_t W_BRB1_3_2_AXID;
+ drex_w_brb1_5_4_axid_t W_BRB1_5_4_AXID;
+ drex_w_brb1_7_6_axid_t W_BRB1_7_6_AXID;
+ ro_bf_t reserved_0x5D0_0x6FC[76];
+ drex_phy_upd_state_t PHY_UPD_STATE;
+ drex_train_state_t TRAIN_STATE;
+} drex_regs_t;
+
+#endif /* _CPU_SAMSUNG_EXYNOS7_DREX_H_ */
diff --git a/src/soc/samsung/exynos7/include/soc/phy.h b/src/soc/samsung/exynos7/include/soc/phy.h
new file mode 100644
index 0000000..6746cce
--- /dev/null
+++ b/src/soc/samsung/exynos7/include/soc/phy.h
@@ -0,0 +1,2033 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _CPU_SAMSUNG_EXYNOS7_PHY_H_
+#define _CPU_SAMSUNG_EXYNOS7_PHY_H_
+
+typedef volatile unsigned int rw_bf_t;
+typedef const unsigned int ro_bf_t;
+typedef const unsigned int wo_bf_t;
+
+typedef struct {
+ rw_bf_t ctrl_rdlat : ( 5 - 0 + 1 );
+ rw_bf_t ctrl_cmosrcv : ( 6 - 6 + 1 );
+ rw_bf_t ctrl_ckdis : ( 7 - 7 + 1 );
+ rw_bf_t ctrl_bstlen : ( 13 - 8 + 1 );
+ rw_bf_t ctrl_otf_bl : ( 14 - 14 + 1 );
+ rw_bf_t ctrl_twpre : ( 15 - 15 + 1 );
+ rw_bf_t ctrl_wrlat : ( 20 - 16 + 1 );
+ ro_bf_t reserved_21_23 : ( 23 - 21 + 1 );
+ rw_bf_t ctrl_ddr_mode : ( 25 - 24 + 1 );
+ rw_bf_t ctrl_dfdqs : ( 26 - 26 + 1 );
+ ro_bf_t reserved_27 : ( 27 - 27 + 1 );
+ rw_bf_t ctrl_upd_range : ( 29 - 28 + 1 );
+ rw_bf_t ctrl_upd_time : ( 31 - 30 + 1 );
+} phy_gnr_con0_t;
+
+typedef struct {
+ rw_bf_t wrlvl_mode : ( 0 - 0 + 1 );
+ rw_bf_t gate_cal_mode : ( 1 - 1 + 1 );
+ rw_bf_t ca_cal_mode : ( 2 - 2 + 1 );
+ rw_bf_t rd_cal_mode : ( 3 - 3 + 1 );
+ ro_bf_t reserved_4 : ( 4 - 4 + 1 );
+ rw_bf_t wr_cal_mode : ( 5 - 5 + 1 );
+ ro_bf_t reserved_6_7 : ( 7 - 6 + 1 );
+ rw_bf_t wrlvl_start : ( 8 - 8 + 1 );
+ ro_bf_t reserved_9_15 : ( 15 - 9 + 1 );
+ ro_bf_t wrlvl_rep : ( 16 - 16 + 1 );
+ ro_bf_t reserved_17_18 : ( 18 - 17 + 1 );
+ rw_bf_t ctrl_dqs_osc_en : ( 19 - 19 + 1 );
+ rw_bf_t byte_rdlvl_en : ( 20 - 20 + 1 );
+ rw_bf_t ca_swap_mode : ( 21 - 21 + 1 );
+ rw_bf_t cal_vtc_en : ( 22 - 22 + 1 );
+ rw_bf_t freq_offset_en : ( 23 - 23 + 1 );
+ rw_bf_t dgate_en : ( 24 - 24 + 1 );
+ rw_bf_t fastdeskewen : ( 25 - 25 + 1 );
+ ro_bf_t reserved_26 : ( 26 - 26 + 1 );
+ rw_bf_t gate_rdchk_en : ( 27 - 27 + 1 );
+ rw_bf_t fine_train_en : ( 28 - 28 + 1 );
+ rw_bf_t wr_per_rank_en : ( 29 - 29 + 1 );
+ rw_bf_t wr_cs_n_default : ( 31 - 30 + 1 );
+} phy_cal_con0_t;
+
+typedef struct {
+ rw_bf_t rdlvl_periodic_incr_adj : ( 6 - 0 + 1 );
+ ro_bf_t reserved_7 : ( 7 - 7 + 1 );
+ rw_bf_t glvl_periodic_incr_adj : ( 14 - 8 + 1 );
+ ro_bf_t reserved_15 : ( 15 - 15 + 1 );
+ rw_bf_t rdlvl_pass_adj : ( 19 - 16 + 1 );
+ rw_bf_t rdlvl_incr_adj : ( 26 - 20 + 1 );
+ ro_bf_t reserved_27 : ( 27 - 27 + 1 );
+ rw_bf_t rdlvl_start_adj : ( 31 - 28 + 1 );
+} phy_cal_con1_t;
+
+typedef struct {
+ ro_bf_t reserved_0_11 : ( 11 - 0 + 1 );
+ rw_bf_t ctrl_readadj : ( 15 - 12 + 1 );
+ rw_bf_t ctrl_readduradj : ( 19 - 16 + 1 );
+ rw_bf_t ctrl_gateadj : ( 23 - 20 + 1 );
+ rw_bf_t ctrl_gateduradj : ( 27 - 24 + 1 );
+ ro_bf_t reserved_28 : ( 28 - 28 + 1 );
+ rw_bf_t ctrl_shgate : ( 29 - 29 + 1 );
+ rw_bf_t ctrl_rodt_disable : ( 30 - 30 + 1 );
+ rw_bf_t ctrl_rpre_opt : ( 31 - 31 + 1 );
+} phy_cal_con2_t;
+
+typedef struct {
+ rw_bf_t pcfg_mode : ( 2 - 0 + 1 );
+ ro_bf_t reserved_3_7 : ( 7 - 3 + 1 );
+ rw_bf_t rd_sw_mode : ( 8 - 8 + 1 );
+ rw_bf_t wr_sw_mode : ( 9 - 9 + 1 );
+ ro_bf_t reserved_10_11 : ( 11 - 10 + 1 );
+ rw_bf_t upd_ack_cycle : ( 14 - 12 + 1 );
+ ro_bf_t reserved_15 : ( 15 - 15 + 1 );
+ rw_bf_t upd_req_cycle : ( 19 - 16 + 1 );
+ rw_bf_t dvfs_wait_cycle : ( 23 - 20 + 1 );
+ rw_bf_t phyupd_req_cycle : ( 28 - 24 + 1 );
+ ro_bf_t reserved_29_31 : ( 31 - 29 + 1 );
+} phy_cal_con3_t;
+
+typedef struct {
+ rw_bf_t ctrl_wrlat_plus0 : ( 2 - 0 + 1 );
+ rw_bf_t ctrl_wrlat_plus1 : ( 5 - 3 + 1 );
+ rw_bf_t ctrl_wrlat_plus2 : ( 8 - 6 + 1 );
+ rw_bf_t ctrl_wrlat_plus3 : ( 11 - 9 + 1 );
+ rw_bf_t ctrl_wrlat_plus4 : ( 14 - 12 + 1 );
+ rw_bf_t ctrl_wrlat_plus5 : ( 17 - 15 + 1 );
+ rw_bf_t ctrl_wrlat_plus6 : ( 20 - 18 + 1 );
+ rw_bf_t ctrl_wrlat_plus7 : ( 23 - 21 + 1 );
+ rw_bf_t ctrl_wrlat_plus8 : ( 26 - 24 + 1 );
+ rw_bf_t ctrl_wrlat_plus9 : ( 27 - 27 + 1 );
+ ro_bf_t reserved_28_31 : ( 31 - 28 + 1 );
+} phy_wlat_con0_t;
+
+typedef struct {
+ rw_bf_t ctrl_pulld_dqs : ( 11 - 0 + 1 );
+ rw_bf_t pcl_pd : ( 12 - 12 + 1 );
+ rw_bf_t ds_pd : ( 13 - 13 + 1 );
+ rw_bf_t ds_io_pd : ( 14 - 14 + 1 );
+ rw_bf_t cs_io_pd : ( 15 - 15 + 1 );
+ ro_bf_t reserved_16_31 : ( 31 - 16 + 1 );
+} phy_lp_con0_t;
+
+typedef struct {
+ rw_bf_t rank0_dsen : ( 1 - 0 + 1 );
+ ro_bf_t reserved_2_11 : ( 11 - 2 + 1 );
+ rw_bf_t rank1_dsen : ( 13 - 12 + 1 );
+ ro_bf_t reserved_14_23 : ( 23 - 14 + 1 );
+ rw_bf_t rank_en : ( 25 - 24 + 1 );
+ ro_bf_t reserved_26_31 : ( 31 - 26 + 1 );
+} phy_gate_con0_t;
+
+typedef struct {
+ rw_bf_t ctrl_offsetr0 : ( 7 - 0 + 1 );
+ rw_bf_t ctrl_offsetr1 : ( 15 - 8 + 1 );
+ rw_bf_t ctrl_offsetr2 : ( 23 - 16 + 1 );
+ rw_bf_t ctrl_offsetr3 : ( 31 - 24 + 1 );
+} phy_offsetr_con0_t;
+
+typedef struct {
+ ro_bf_t reserved_0_7 : ( 7 - 0 + 1 );
+ rw_bf_t ctrl_offsetr5 : ( 15 - 8 + 1 );
+ rw_bf_t ctrl_offsetr6 : ( 23 - 16 + 1 );
+ rw_bf_t ctrl_offsetr7 : ( 31 - 24 + 1 );
+} phy_offsetr_con1_t;
+
+typedef struct {
+ rw_bf_t ctrl_offsetr8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_offsetr_con2_t;
+
+typedef struct {
+ rw_bf_t ctrl_dq_lat_ds0 : ( 0 - 0 + 1 );
+ rw_bf_t ctrl_dq_lat_ds1 : ( 1 - 1 + 1 );
+ rw_bf_t ctrl_dq_lat_ds2 : ( 2 - 2 + 1 );
+ rw_bf_t ctrl_dq_lat_ds3 : ( 3 - 3 + 1 );
+ rw_bf_t ctrl_dq_lat_ds4 : ( 4 - 4 + 1 );
+ rw_bf_t ctrl_dq_lat_ds5 : ( 5 - 5 + 1 );
+ rw_bf_t ctrl_dq_lat_ds6 : ( 6 - 6 + 1 );
+ rw_bf_t ctrl_dq_lat_ds7 : ( 7 - 7 + 1 );
+ rw_bf_t ctrl_dq_lat_ds8 : ( 8 - 8 + 1 );
+ ro_bf_t reserved_9_31 : ( 31 - 9 + 1 );
+} phy_dqlat_con0_t;
+
+typedef struct {
+ rw_bf_t ctrl_offsetw0 : ( 7 - 0 + 1 );
+ rw_bf_t ctrl_offsetw1 : ( 15 - 8 + 1 );
+ rw_bf_t ctrl_offsetw2 : ( 23 - 16 + 1 );
+ rw_bf_t ctrl_offsetw3 : ( 31 - 24 + 1 );
+} phy_offsetw_con0_t;
+
+typedef struct {
+ rw_bf_t ctrl_offsetw4 : ( 7 - 0 + 1 );
+ rw_bf_t ctrl_offsetw5 : ( 15 - 8 + 1 );
+ rw_bf_t ctrl_offsetw6 : ( 23 - 16 + 1 );
+ rw_bf_t ctrl_offsetw7 : ( 31 - 24 + 1 );
+} phy_offsetw_con1_t;
+
+typedef struct {
+ rw_bf_t ctrl_offsetw8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_offsetw_con2_t;
+
+typedef struct {
+ rw_bf_t ctrl_offsetr_dq : ( 5 - 0 + 1 );
+ ro_bf_t reserved_6_31 : ( 31 - 6 + 1 );
+} phy_offset_dq_con0_t;
+
+typedef struct {
+ rw_bf_t ctrl_offsetc0 : ( 7 - 0 + 1 );
+ rw_bf_t ctrl_offsetc1 : ( 15 - 8 + 1 );
+ rw_bf_t ctrl_offsetc2 : ( 23 - 16 + 1 );
+ rw_bf_t ctrl_offsetc3 : ( 31 - 24 + 1 );
+} phy_offsetc_con0_t;
+
+typedef struct {
+ rw_bf_t ctrl_offsetc4 : ( 7 - 0 + 1 );
+ rw_bf_t ctrl_offsetc5 : ( 15 - 8 + 1 );
+ rw_bf_t ctrl_offsetc6 : ( 23 - 16 + 1 );
+ rw_bf_t ctrl_offsetc7 : ( 31 - 24 + 1 );
+} phy_offsetc_con1_t;
+
+typedef struct {
+ rw_bf_t ctrl_offsetc8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_offsetc_con2_t;
+
+typedef struct {
+ rw_bf_t ctrl_shiftc0 : ( 2 - 0 + 1 );
+ rw_bf_t ctrl_shiftc1 : ( 5 - 3 + 1 );
+ rw_bf_t ctrl_shiftc2 : ( 8 - 6 + 1 );
+ rw_bf_t ctrl_shiftc3 : ( 11 - 9 + 1 );
+ rw_bf_t ctrl_shiftc4 : ( 14 - 12 + 1 );
+ rw_bf_t ctrl_shiftc5 : ( 17 - 15 + 1 );
+ rw_bf_t ctrl_shiftc6 : ( 20 - 18 + 1 );
+ rw_bf_t ctrl_shiftc7 : ( 23 - 21 + 1 );
+ rw_bf_t ctrl_shiftc8 : ( 26 - 24 + 1 );
+ ro_bf_t reserved_27_31 : ( 31 - 27 + 1 );
+} phy_shiftc_con0_t;
+
+typedef struct {
+ rw_bf_t ctrl_offsetd : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_23 : ( 23 - 8 + 1 );
+ rw_bf_t ctrl_resync : ( 24 - 24 + 1 );
+ ro_bf_t reserved_25_27 : ( 27 - 25 + 1 );
+ rw_bf_t upd_mode : ( 28 - 28 + 1 );
+ ro_bf_t reserved_29_31 : ( 31 - 29 + 1 );
+} phy_offsetd_con0_t;
+
+typedef struct {
+ rw_bf_t ctrl_offseto0 : ( 7 - 0 + 1 );
+ rw_bf_t ctrl_offseto1 : ( 15 - 8 + 1 );
+ rw_bf_t ctrl_offseto2 : ( 23 - 16 + 1 );
+ rw_bf_t ctrl_offseto3 : ( 31 - 24 + 1 );
+} phy_offseto_con0_t;
+
+typedef struct {
+ rw_bf_t ctrl_offseto4 : ( 7 - 0 + 1 );
+ rw_bf_t ctrl_offseto5 : ( 15 - 8 + 1 );
+ rw_bf_t ctrl_offseto6 : ( 23 - 16 + 1 );
+ rw_bf_t ctrl_offseto7 : ( 31 - 24 + 1 );
+} phy_offseto_con1_t;
+
+typedef struct {
+ ro_bf_t reserved_0_23 : ( 23 - 0 + 1 );
+ rw_bf_t ctrl_offseto8 : ( 31 - 24 + 1 );
+} phy_offseto_con2_t;
+
+typedef struct {
+ rw_bf_t ctrl_wrlvl0_code : ( 7 - 0 + 1 );
+ rw_bf_t ctrl_wrlvl1_code : ( 15 - 8 + 1 );
+ rw_bf_t ctrl_wrlvl2_code : ( 23 - 16 + 1 );
+ rw_bf_t ctrl_wrlvl3_code : ( 31 - 24 + 1 );
+} phy_wr_lvl_con0_t;
+
+typedef struct {
+ rw_bf_t ctrl_wrlvl4_code : ( 7 - 0 + 1 );
+ rw_bf_t ctrl_wrlvl5_code : ( 15 - 8 + 1 );
+ rw_bf_t ctrl_wrlvl6_code : ( 23 - 16 + 1 );
+ rw_bf_t ctrl_wrlvl7_code : ( 31 - 24 + 1 );
+} phy_wr_lvl_con1_t;
+
+typedef struct {
+ rw_bf_t ctrl_wrlvl8_code : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_wr_lvl_con2_t;
+
+typedef struct {
+ rw_bf_t ctrl_wrlvl_resync : ( 0 - 0 + 1 );
+ ro_bf_t reserved_1_31 : ( 31 - 1 + 1 );
+} phy_wr_lvl_con3_t;
+
+typedef struct {
+ rw_bf_t ca0deskewcode : ( 7 - 0 + 1 );
+ rw_bf_t ca1deskewcode : ( 15 - 8 + 1 );
+ rw_bf_t ca2deskewcode : ( 23 - 16 + 1 );
+ rw_bf_t ca3deskewcode : ( 31 - 24 + 1 );
+} phy_ca_dskew_con0_t;
+
+typedef struct {
+ rw_bf_t ca4deskewcode : ( 7 - 0 + 1 );
+ rw_bf_t ca5deskewcode : ( 15 - 8 + 1 );
+ rw_bf_t ckdeskewcode : ( 23 - 16 + 1 );
+ rw_bf_t cs0deskewcode : ( 31 - 24 + 1 );
+} phy_ca_dskew_con1_t;
+
+typedef struct {
+ rw_bf_t cs1deskewcode : ( 7 - 0 + 1 );
+ rw_bf_t cke0deskewcode : ( 15 - 8 + 1 );
+ rw_bf_t cke1deskewcode : ( 23 - 16 + 1 );
+ rw_bf_t rsvd0 : ( 31 - 24 + 1 );
+} phy_ca_dskew_con2_t;
+
+typedef struct {
+ rw_bf_t rstdeskewcode : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_ca_dskew_con4_t;
+
+typedef struct {
+ rw_bf_t wrtrn_rddata_adj_w1 : ( 15 - 0 + 1 );
+ rw_bf_t wrtrn_rddata_adj_w0 : ( 31 - 16 + 1 );
+} phy_cal_pattern_con0_t;
+
+typedef struct {
+ rw_bf_t wrtrn_rddata_adj_w3 : ( 15 - 0 + 1 );
+ rw_bf_t wrtrn_rddata_adj_w2 : ( 31 - 16 + 1 );
+} phy_cal_pattern_con1_t;
+
+typedef struct {
+ rw_bf_t wrtrn_rddata_dm_adj_w3 : ( 1 - 0 + 1 );
+ rw_bf_t wrtrn_rddata_dm_adj_w2 : ( 3 - 2 + 1 );
+ rw_bf_t wrtrn_rddata_dm_adj_w1 : ( 5 - 4 + 1 );
+ rw_bf_t wrtrn_rddata_dm_adj_w0 : ( 7 - 6 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_cal_pattern_con2_t;
+
+typedef struct {
+ rw_bf_t rdtrn_rddata_adj_w1 : ( 15 - 0 + 1 );
+ rw_bf_t rdtrn_rddata_adj_w0 : ( 31 - 16 + 1 );
+} phy_cal_pattern_con3_t;
+
+typedef struct {
+ rw_bf_t rdtrn_rddata_adj_w3 : ( 15 - 0 + 1 );
+ rw_bf_t rdtrn_rddata_adj_w2 : ( 31 - 16 + 1 );
+} phy_cal_pattern_con4_t;
+
+typedef struct {
+ rw_bf_t rdtrn_rddata_dm_adj_w3 : ( 1 - 0 + 1 );
+ rw_bf_t rdtrn_rddata_dm_adj_w2 : ( 3 - 2 + 1 );
+ rw_bf_t rdtrn_rddata_dm_adj_w1 : ( 5 - 4 + 1 );
+ rw_bf_t rdtrn_rddata_dm_adj_w0 : ( 7 - 6 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_cal_pattern_con5_t;
+
+typedef struct {
+ rw_bf_t ctrl_half : ( 0 - 0 + 1 );
+ rw_bf_t ctrl_ref : ( 4 - 1 + 1 );
+ rw_bf_t ctrl_dll_on : ( 5 - 5 + 1 );
+ rw_bf_t ctrl_start : ( 6 - 6 + 1 );
+ rw_bf_t ctrl_force : ( 15 - 7 + 1 );
+ rw_bf_t ctrl_inc : ( 22 - 16 + 1 );
+ ro_bf_t reserved_23 : ( 23 - 23 + 1 );
+ rw_bf_t ctrl_start_point : ( 30 - 24 + 1 );
+ ro_bf_t reserved_31 : ( 31 - 31 + 1 );
+} phy_mdll_con0_t;
+
+typedef struct {
+ ro_bf_t ctrl_locked : ( 0 - 0 + 1 );
+ ro_bf_t ctrl_flock : ( 1 - 1 + 1 );
+ ro_bf_t ctrl_clock : ( 2 - 2 + 1 );
+ ro_bf_t harmonic_lock : ( 3 - 3 + 1 );
+ ro_bf_t reserved_4_7 : ( 7 - 4 + 1 );
+ ro_bf_t ctrl_lock_value : ( 16 - 8 + 1 );
+ ro_bf_t reserved_17_21 : ( 21 - 17 + 1 );
+ rw_bf_t lock_value_init_override : ( 22 - 22 + 1 );
+ ro_bf_t ctrl_lock_value_init : ( 31 - 23 + 1 );
+} phy_mdll_con1_t;
+
+typedef struct {
+ rw_bf_t dvfs0_offset : ( 7 - 0 + 1 );
+ rw_bf_t dvfs1_offset : ( 15 - 8 + 1 );
+ rw_bf_t dvfs0_dqs_osc_en : ( 16 - 16 + 1 );
+ rw_bf_t dvfs1_dqs_osc_en : ( 17 - 17 + 1 );
+ rw_bf_t dvfs0_half : ( 18 - 18 + 1 );
+ rw_bf_t dvfs1_half : ( 19 - 19 + 1 );
+ rw_bf_t dvfs0_dll_on : ( 20 - 20 + 1 );
+ rw_bf_t dvfs1_dll_on : ( 21 - 21 + 1 );
+ rw_bf_t dvfs0_rodt_disable : ( 22 - 22 + 1 );
+ rw_bf_t dvfs1_rodt_disable : ( 23 - 23 + 1 );
+ rw_bf_t dvfs_mode : ( 25 - 24 + 1 );
+ ro_bf_t reserved_26_27 : ( 27 - 26 + 1 );
+ rw_bf_t dvfs0_dgatelvl_en : ( 28 - 28 + 1 );
+ rw_bf_t dvfs1_dgatelvl_en : ( 29 - 29 + 1 );
+ rw_bf_t dvfs0_wr_per_rank_en : ( 30 - 30 + 1 );
+ rw_bf_t dvfs1_wr_per_rank_en : ( 31 - 31 + 1 );
+} phy_dvfs_con0_t;
+
+typedef struct {
+ rw_bf_t dvfs0_gateadj : ( 3 - 0 + 1 );
+ rw_bf_t dvfs0_gateduradj : ( 7 - 4 + 1 );
+ rw_bf_t dvfs1_gateadj : ( 11 - 8 + 1 );
+ rw_bf_t dvfs1_gateduradj : ( 15 - 12 + 1 );
+ rw_bf_t dvfs0_rdat : ( 21 - 16 + 1 );
+ ro_bf_t reserved_22_23 : ( 23 - 22 + 1 );
+ rw_bf_t dvfs1_rdat : ( 29 - 24 + 1 );
+ rw_bf_t dvfs0_cmosrcv : ( 30 - 30 + 1 );
+ rw_bf_t dvfs1_cmosrcv : ( 31 - 31 + 1 );
+} phy_dvfs_con1_t;
+
+typedef struct {
+ rw_bf_t freq_train : ( 11 - 0 + 1 );
+ ro_bf_t reserved_12_17 : ( 17 - 12 + 1 );
+ rw_bf_t dvfs0_start_point : ( 24 - 18 + 1 );
+ rw_bf_t dvfs1_start_point : ( 31 - 25 + 1 );
+} phy_dvfs_con2_t;
+
+typedef struct {
+ rw_bf_t dvfs0_freq : ( 11 - 0 + 1 );
+ rw_bf_t dvfs1_freq : ( 23 - 12 + 1 );
+ ro_bf_t reserved_24_25 : ( 25 - 24 + 1 );
+ rw_bf_t dvfs0_shgate : ( 26 - 26 + 1 );
+ rw_bf_t dvfs1_shgate : ( 27 - 27 + 1 );
+ rw_bf_t dvfs0_rpre_opt : ( 28 - 28 + 1 );
+ rw_bf_t dvfs1_rpre_opt : ( 29 - 29 + 1 );
+ rw_bf_t dvfs0_twpre : ( 30 - 30 + 1 );
+ rw_bf_t dvfs1_twpre : ( 31 - 31 + 1 );
+} phy_dvfs_con3_t;
+
+typedef struct {
+ rw_bf_t dvfs0_ds0_vref : ( 5 - 0 + 1 );
+ rw_bf_t dvfs0_ds1_vref : ( 11 - 6 + 1 );
+ rw_bf_t dvfs1_ds0_vref : ( 17 - 12 + 1 );
+ rw_bf_t dvfs1_ds1_vref : ( 23 - 18 + 1 );
+ ro_bf_t reserved_24_30 : ( 30 - 24 + 1 );
+ rw_bf_t dvfs_fsbst_en : ( 31 - 31 + 1 );
+} phy_dvfs_con4_t;
+
+typedef struct {
+ rw_bf_t dvfs0_pulld_dqs : ( 3 - 0 + 1 );
+ rw_bf_t dvfs1_pulld_dqs : ( 7 - 4 + 1 );
+ rw_bf_t dvfs0_readadj : ( 11 - 8 + 1 );
+ rw_bf_t dvfs1_readadj : ( 15 - 12 + 1 );
+ rw_bf_t dvfs0_readduradj : ( 19 - 16 + 1 );
+ rw_bf_t dvfs1_readduradj : ( 23 - 20 + 1 );
+ ro_bf_t reserved_24_31 : ( 31 - 24 + 1 );
+} phy_dvfs_con5_t;
+
+typedef struct {
+ ro_bf_t t0_rdata_en : ( 5 - 0 + 1 );
+ ro_bf_t t1_rdata_en : ( 11 - 6 + 1 );
+ ro_bf_t t2_rdata_en : ( 17 - 12 + 1 );
+ ro_bf_t t3_rdata_en : ( 23 - 18 + 1 );
+ ro_bf_t t_rddata_en : ( 28 - 24 + 1 );
+ ro_bf_t reserved_29_31 : ( 31 - 29 + 1 );
+} phy_t_rddata_con0_t;
+
+typedef struct {
+ ro_bf_t t4_rdata_en : ( 5 - 0 + 1 );
+ ro_bf_t t5_rdata_en : ( 11 - 6 + 1 );
+ ro_bf_t t6_rdata_en : ( 17 - 12 + 1 );
+ ro_bf_t t7_rdata_en : ( 23 - 18 + 1 );
+ ro_bf_t reserved_24_31 : ( 31 - 24 + 1 );
+} phy_t_rddata_con1_t;
+
+typedef struct {
+ ro_bf_t t8_rdata_en : ( 5 - 0 + 1 );
+ ro_bf_t reserved_6_31 : ( 31 - 6 + 1 );
+} phy_t_rddata_con2_t;
+
+typedef struct {
+ ro_bf_t dq_fail_status_sl0 : ( 7 - 0 + 1 );
+ ro_bf_t dq_fail_status_sl1 : ( 15 - 8 + 1 );
+ ro_bf_t dq_fail_status_sl2 : ( 23 - 16 + 1 );
+ ro_bf_t dq_fail_status_sl3 : ( 31 - 24 + 1 );
+} phy_cal_fail_stat0_t;
+
+typedef struct {
+ ro_bf_t dq_fail_status_sl4 : ( 7 - 0 + 1 );
+ ro_bf_t dq_fail_status_sl5 : ( 15 - 8 + 1 );
+ ro_bf_t dq_fail_status_sl6 : ( 23 - 16 + 1 );
+ ro_bf_t dq_fail_status_sl7 : ( 31 - 24 + 1 );
+} phy_cal_fail_stat1_t;
+
+typedef struct {
+ ro_bf_t dq_fail_status_sl8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_cal_fail_stat2_t;
+
+typedef struct {
+ ro_bf_t dm_fail_status : ( 8 - 0 + 1 );
+ ro_bf_t reserved_9_31 : ( 31 - 9 + 1 );
+} phy_cal_fail_stat3_t;
+
+typedef struct {
+ ro_bf_t gt_vwmc0_cs0 : ( 7 - 0 + 1 );
+ ro_bf_t gt_vwmc1_cs0 : ( 15 - 8 + 1 );
+ ro_bf_t gt_vwmc2_cs0 : ( 23 - 16 + 1 );
+ ro_bf_t gt_vwmc3_cs0 : ( 31 - 24 + 1 );
+} phy_cal_gt_wvmc0_t;
+
+typedef struct {
+ ro_bf_t gt_vwmc4_cs0 : ( 7 - 0 + 1 );
+ ro_bf_t gt_vwmc5_cs0 : ( 15 - 8 + 1 );
+ ro_bf_t gt_vwmc6_cs0 : ( 23 - 16 + 1 );
+ ro_bf_t gt_vwmc7_cs0 : ( 31 - 24 + 1 );
+} phy_cal_gt_wvmc1_t;
+
+typedef struct {
+ ro_bf_t gt_vwmc8_cs0 : ( 7 - 0 + 1 );
+ ro_bf_t rsvd0 : ( 31 - 8 + 1 );
+} phy_cal_gt_wvmc2_t;
+
+typedef struct {
+ ro_bf_t gt_cyc0_cs0 : ( 2 - 0 + 1 );
+ ro_bf_t reserved_3_7 : ( 7 - 3 + 1 );
+ ro_bf_t gt_cyc1_cs0 : ( 10 - 8 + 1 );
+ ro_bf_t reserved_11_31 : ( 31 - 11 + 1 );
+} phy_cal_gt_cyc_t;
+
+typedef struct {
+ ro_bf_t rd_vwmc0 : ( 7 - 0 + 1 );
+ ro_bf_t rd_vwmc1 : ( 15 - 8 + 1 );
+ ro_bf_t rd_vwmc2 : ( 23 - 16 + 1 );
+ ro_bf_t rd_vwmc3 : ( 31 - 24 + 1 );
+} phy_cal_rd_vwmc0_t;
+
+typedef struct {
+ ro_bf_t rd_vwmc4 : ( 7 - 0 + 1 );
+ ro_bf_t rd_vwmc5 : ( 15 - 8 + 1 );
+ ro_bf_t rd_vwmc6 : ( 23 - 16 + 1 );
+ ro_bf_t rd_vwmc7 : ( 31 - 24 + 1 );
+} phy_cal_rd_vwmc1_t;
+
+typedef struct {
+ ro_bf_t rd_vwmc8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_cal_rd_vwmc2_t;
+
+typedef struct {
+ ro_bf_t rd_vwml0 : ( 7 - 0 + 1 );
+ ro_bf_t rd_vwml1 : ( 15 - 8 + 1 );
+ ro_bf_t rd_vwml2 : ( 23 - 16 + 1 );
+ ro_bf_t rd_vwml3 : ( 31 - 24 + 1 );
+} phy_cal_rd_vwml0_t;
+
+typedef struct {
+ ro_bf_t rd_vwml4 : ( 7 - 0 + 1 );
+ ro_bf_t rd_vwml5 : ( 15 - 8 + 1 );
+ ro_bf_t rd_vwml6 : ( 23 - 16 + 1 );
+ ro_bf_t rd_vwml7 : ( 31 - 24 + 1 );
+} phy_cal_rd_vwml1_t;
+
+typedef struct {
+ ro_bf_t rd_vwmc8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_cal_rd_vwml2_t;
+
+typedef struct {
+ ro_bf_t rd_vwmr0 : ( 7 - 0 + 1 );
+ ro_bf_t rd_vwmr1 : ( 15 - 8 + 1 );
+ ro_bf_t rd_vwmr2 : ( 23 - 16 + 1 );
+ ro_bf_t rd_vwmr3 : ( 31 - 24 + 1 );
+} phy_cal_rd_vwmr0_t;
+
+typedef struct {
+ ro_bf_t rd_vwmr4 : ( 7 - 0 + 1 );
+ ro_bf_t rd_vwmr5 : ( 15 - 8 + 1 );
+ ro_bf_t rd_vwmr6 : ( 23 - 16 + 1 );
+ ro_bf_t rd_vwmr7 : ( 31 - 24 + 1 );
+} phy_cal_rd_vwmr1_t;
+
+typedef struct {
+ ro_bf_t rd_vwmr8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_cal_rd_vwmr2_t;
+
+typedef struct {
+ ro_bf_t wr_vwmc0 : ( 7 - 0 + 1 );
+ ro_bf_t wr_vwmc1 : ( 15 - 8 + 1 );
+ ro_bf_t wr_vwmc2 : ( 23 - 16 + 1 );
+ ro_bf_t wr_vwmc3 : ( 31 - 24 + 1 );
+} phy_cal_wr_vwmc0_t;
+
+typedef struct {
+ ro_bf_t wr_vwmc4 : ( 7 - 0 + 1 );
+ ro_bf_t wr_vwmc5 : ( 15 - 8 + 1 );
+ ro_bf_t wr_vwmc6 : ( 23 - 16 + 1 );
+ ro_bf_t wr_vwmc7 : ( 31 - 24 + 1 );
+} phy_cal_wr_vwmc1_t;
+
+typedef struct {
+ ro_bf_t wr_vwmc8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_cal_wr_vwmc2_t;
+
+typedef struct {
+ ro_bf_t wr_vwml0 : ( 7 - 0 + 1 );
+ ro_bf_t wr_vwml1 : ( 15 - 8 + 1 );
+ ro_bf_t wr_vwml2 : ( 23 - 16 + 1 );
+ ro_bf_t wr_vwml3 : ( 31 - 24 + 1 );
+} phy_cal_wr_vwml0_t;
+
+typedef struct {
+ ro_bf_t wr_vwml4 : ( 7 - 0 + 1 );
+ ro_bf_t wr_vwml5 : ( 15 - 8 + 1 );
+ ro_bf_t wr_vwml6 : ( 23 - 16 + 1 );
+ ro_bf_t wr_vwml7 : ( 31 - 24 + 1 );
+} phy_cal_wr_vwml1_t;
+
+typedef struct {
+ ro_bf_t wr_vwml8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_cal_wr_vwml2_t;
+
+typedef struct {
+ ro_bf_t wr_vwmr0 : ( 7 - 0 + 1 );
+ ro_bf_t wr_vwmr1 : ( 15 - 8 + 1 );
+ ro_bf_t wr_vwmr2 : ( 23 - 16 + 1 );
+ ro_bf_t wr_vwmr3 : ( 31 - 24 + 1 );
+} phy_cal_wr_vwmr0_t;
+
+typedef struct {
+ ro_bf_t wr_vwmr4 : ( 7 - 0 + 1 );
+ ro_bf_t wr_vwmr5 : ( 15 - 8 + 1 );
+ ro_bf_t wr_vwmr6 : ( 23 - 16 + 1 );
+ ro_bf_t wr_vwmr7 : ( 31 - 24 + 1 );
+} phy_cal_wr_vwmr1_t;
+
+typedef struct {
+ ro_bf_t wr_vwmr8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_cal_wr_vwmr2_t;
+
+typedef struct {
+ ro_bf_t wr_vwmc0 : ( 7 - 0 + 1 );
+ ro_bf_t wr_vwmc1 : ( 15 - 8 + 1 );
+ ro_bf_t wr_vwmc2 : ( 23 - 16 + 1 );
+ ro_bf_t wr_vwmc3 : ( 31 - 24 + 1 );
+} phy_cal_dm_vwmc0_t;
+
+typedef struct {
+ ro_bf_t wr_vwmc4 : ( 7 - 0 + 1 );
+ ro_bf_t wr_vwmc5 : ( 15 - 8 + 1 );
+ ro_bf_t wr_vwmc6 : ( 23 - 16 + 1 );
+ ro_bf_t wr_vwmc7 : ( 31 - 24 + 1 );
+} phy_cal_dm_vwmc1_t;
+
+typedef struct {
+ ro_bf_t wr_vwmc8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_cal_dm_vwmc2_t;
+
+typedef struct {
+ ro_bf_t wr_vwml0 : ( 7 - 0 + 1 );
+ ro_bf_t wr_vwml1 : ( 15 - 8 + 1 );
+ ro_bf_t wr_vwml2 : ( 23 - 16 + 1 );
+ ro_bf_t wr_vwml3 : ( 31 - 24 + 1 );
+} phy_cal_dm_vwml0_t;
+
+typedef struct {
+ ro_bf_t wr_vwml4 : ( 7 - 0 + 1 );
+ ro_bf_t wr_vwml5 : ( 15 - 8 + 1 );
+ ro_bf_t wr_vwml6 : ( 23 - 16 + 1 );
+ ro_bf_t wr_vwml7 : ( 31 - 24 + 1 );
+} phy_cal_dm_vwml1_t;
+
+typedef struct {
+ ro_bf_t wr_vwml8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_cal_dm_vwml2_t;
+
+typedef struct {
+ ro_bf_t wr_vwmr0 : ( 7 - 0 + 1 );
+ ro_bf_t wr_vwmr1 : ( 15 - 8 + 1 );
+ ro_bf_t wr_vwmr2 : ( 23 - 16 + 1 );
+ ro_bf_t wr_vwmr3 : ( 31 - 24 + 1 );
+} phy_cal_dm_vwmr0_t;
+
+typedef struct {
+ ro_bf_t wr_vwmr4 : ( 7 - 0 + 1 );
+ ro_bf_t wr_vwmr5 : ( 15 - 8 + 1 );
+ ro_bf_t wr_vwmr6 : ( 23 - 16 + 1 );
+ ro_bf_t wr_vwmr7 : ( 31 - 24 + 1 );
+} phy_cal_dm_vwmr1_t;
+
+typedef struct {
+ ro_bf_t wr_vwmr8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_cal_dm_vwmr2_t;
+
+typedef struct {
+ ro_bf_t rd0deskew0 : ( 7 - 0 + 1 );
+ ro_bf_t rd0deskew1 : ( 15 - 8 + 1 );
+ ro_bf_t rd0deskew2 : ( 23 - 16 + 1 );
+ ro_bf_t rd0deskew3 : ( 31 - 24 + 1 );
+} phy_rd_deskew_con0_t;
+
+typedef struct {
+ ro_bf_t rd0deskew4 : ( 7 - 0 + 1 );
+ ro_bf_t rd0deskew5 : ( 15 - 8 + 1 );
+ ro_bf_t rd0deskew6 : ( 23 - 16 + 1 );
+ ro_bf_t rd0deskew7 : ( 31 - 24 + 1 );
+} phy_rd_deskew_con1_t;
+
+typedef struct {
+ ro_bf_t rd0deskew8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_rd_deskew_con2_t;
+
+typedef struct {
+ ro_bf_t rd1deskew0 : ( 7 - 0 + 1 );
+ ro_bf_t rd1deskew1 : ( 15 - 8 + 1 );
+ ro_bf_t rd1deskew2 : ( 23 - 16 + 1 );
+ ro_bf_t rd1deskew3 : ( 31 - 24 + 1 );
+} phy_rd_deskew_con3_t;
+
+typedef struct {
+ ro_bf_t rd1deskew4 : ( 7 - 0 + 1 );
+ ro_bf_t rd1deskew5 : ( 15 - 8 + 1 );
+ ro_bf_t rd1deskew6 : ( 23 - 16 + 1 );
+ ro_bf_t rd1deskew7 : ( 31 - 24 + 1 );
+} phy_rd_deskew_con4_t;
+
+typedef struct {
+ ro_bf_t rd1deskew8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_rd_deskew_con5_t;
+
+typedef struct {
+ ro_bf_t rd2deskew0 : ( 7 - 0 + 1 );
+ ro_bf_t rd2deskew1 : ( 15 - 8 + 1 );
+ ro_bf_t rd2deskew2 : ( 23 - 16 + 1 );
+ ro_bf_t rd2deskew3 : ( 31 - 24 + 1 );
+} phy_rd_deskew_con6_t;
+
+typedef struct {
+ ro_bf_t rd2deskew4 : ( 7 - 0 + 1 );
+ ro_bf_t rd2deskew5 : ( 15 - 8 + 1 );
+ ro_bf_t rd2deskew6 : ( 23 - 16 + 1 );
+ ro_bf_t rd2deskew7 : ( 31 - 24 + 1 );
+} phy_rd_deskew_con7_t;
+
+typedef struct {
+ ro_bf_t rd2deskew8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_rd_deskew_con8_t;
+
+typedef struct {
+ ro_bf_t rd3deskew0 : ( 7 - 0 + 1 );
+ ro_bf_t rd3deskew1 : ( 15 - 8 + 1 );
+ ro_bf_t rd3deskew2 : ( 23 - 16 + 1 );
+ ro_bf_t rd3deskew3 : ( 31 - 24 + 1 );
+} phy_rd_deskew_con9_t;
+
+typedef struct {
+ ro_bf_t rd3deskew4 : ( 7 - 0 + 1 );
+ ro_bf_t rd3deskew5 : ( 15 - 8 + 1 );
+ ro_bf_t rd3deskew6 : ( 23 - 16 + 1 );
+ ro_bf_t rd3deskew7 : ( 31 - 24 + 1 );
+} phy_rd_deskew_con10_t;
+
+typedef struct {
+ ro_bf_t rd4deskew8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_rd_deskew_con11_t;
+
+typedef struct {
+ ro_bf_t rd4deskew0 : ( 7 - 0 + 1 );
+ ro_bf_t rd4deskew1 : ( 15 - 8 + 1 );
+ ro_bf_t rd4deskew2 : ( 23 - 16 + 1 );
+ ro_bf_t rd4deskew3 : ( 31 - 24 + 1 );
+} phy_rd_deskew_con12_t;
+
+typedef struct {
+ ro_bf_t rd4deskew4 : ( 7 - 0 + 1 );
+ ro_bf_t rd4deskew5 : ( 15 - 8 + 1 );
+ ro_bf_t rd4deskew6 : ( 23 - 16 + 1 );
+ ro_bf_t rd4deskew7 : ( 31 - 24 + 1 );
+} phy_rd_deskew_con13_t;
+
+typedef struct {
+ ro_bf_t rd4deskew8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_rd_deskew_con14_t;
+
+typedef struct {
+ ro_bf_t rd5deskew0 : ( 7 - 0 + 1 );
+ ro_bf_t rd5deskew1 : ( 15 - 8 + 1 );
+ ro_bf_t rd5deskew2 : ( 23 - 16 + 1 );
+ ro_bf_t rd5deskew3 : ( 31 - 24 + 1 );
+} phy_rd_deskew_con15_t;
+
+typedef struct {
+ ro_bf_t rd5deskew4 : ( 7 - 0 + 1 );
+ ro_bf_t rd5deskew5 : ( 15 - 8 + 1 );
+ ro_bf_t rd5deskew6 : ( 23 - 16 + 1 );
+ ro_bf_t rd5deskew7 : ( 31 - 24 + 1 );
+} phy_rd_deskew_con16_t;
+
+typedef struct {
+ ro_bf_t rd5deskew8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_rd_deskew_con17_t;
+
+typedef struct {
+ ro_bf_t rd6deskew0 : ( 7 - 0 + 1 );
+ ro_bf_t rd6deskew1 : ( 15 - 8 + 1 );
+ ro_bf_t rd6deskew2 : ( 23 - 16 + 1 );
+ ro_bf_t rd6deskew3 : ( 31 - 24 + 1 );
+} phy_rd_deskew_con18_t;
+
+typedef struct {
+ ro_bf_t rd6deskew4 : ( 7 - 0 + 1 );
+ ro_bf_t rd6deskew5 : ( 15 - 8 + 1 );
+ ro_bf_t rd6deskew6 : ( 23 - 16 + 1 );
+ ro_bf_t rd6deskew7 : ( 31 - 24 + 1 );
+} phy_rd_deskew_con19_t;
+
+typedef struct {
+ ro_bf_t rd6deskew8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_rd_deskew_con20_t;
+
+typedef struct {
+ ro_bf_t rd7deskew0 : ( 7 - 0 + 1 );
+ ro_bf_t rd7deskew1 : ( 15 - 8 + 1 );
+ ro_bf_t rd7deskew2 : ( 23 - 16 + 1 );
+ ro_bf_t rd7deskew3 : ( 31 - 24 + 1 );
+} phy_rd_deskew_con21_t;
+
+typedef struct {
+ ro_bf_t rd7deskew4 : ( 7 - 0 + 1 );
+ ro_bf_t rd7deskew5 : ( 15 - 8 + 1 );
+ ro_bf_t rd7deskew6 : ( 23 - 16 + 1 );
+ ro_bf_t rd7deskew7 : ( 31 - 24 + 1 );
+} phy_rd_deskew_con22_t;
+
+typedef struct {
+ ro_bf_t rd7deskew8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_rd_deskew_con23_t;
+
+typedef struct {
+ ro_bf_t wr0deskew0 : ( 7 - 0 + 1 );
+ ro_bf_t wr0deskew1 : ( 15 - 8 + 1 );
+ ro_bf_t wr0deskew2 : ( 23 - 16 + 1 );
+ ro_bf_t wr0deskew3 : ( 31 - 24 + 1 );
+} phy_wr_deskew_con0_t;
+
+typedef struct {
+ ro_bf_t wr0deskew4 : ( 7 - 0 + 1 );
+ ro_bf_t wr0deskew5 : ( 15 - 8 + 1 );
+ ro_bf_t wr0deskew6 : ( 23 - 16 + 1 );
+ ro_bf_t wr0deskew7 : ( 31 - 24 + 1 );
+} phy_wr_deskew_con1_t;
+
+typedef struct {
+ ro_bf_t wr0deskew8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_wr_deskew_con2_t;
+
+typedef struct {
+ ro_bf_t wr1deskew0 : ( 7 - 0 + 1 );
+ ro_bf_t wr1deskew1 : ( 15 - 8 + 1 );
+ ro_bf_t wr1deskew2 : ( 23 - 16 + 1 );
+ ro_bf_t wr1deskew3 : ( 31 - 24 + 1 );
+} phy_wr_deskew_con3_t;
+
+typedef struct {
+ ro_bf_t wr1deskew4 : ( 7 - 0 + 1 );
+ ro_bf_t wr1deskew5 : ( 15 - 8 + 1 );
+ ro_bf_t wr1deskew6 : ( 23 - 16 + 1 );
+ ro_bf_t wr1deskew7 : ( 31 - 24 + 1 );
+} phy_wr_deskew_con4_t;
+
+typedef struct {
+ ro_bf_t wr1deskew8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_wr_deskew_con5_t;
+
+typedef struct {
+ ro_bf_t wr2deskew0 : ( 7 - 0 + 1 );
+ ro_bf_t wr2deskew1 : ( 15 - 8 + 1 );
+ ro_bf_t wr2deskew2 : ( 23 - 16 + 1 );
+ ro_bf_t wr2deskew3 : ( 31 - 24 + 1 );
+} phy_wr_deskew_con6_t;
+
+typedef struct {
+ ro_bf_t wr2deskew4 : ( 7 - 0 + 1 );
+ ro_bf_t wr2deskew5 : ( 15 - 8 + 1 );
+ ro_bf_t wr2deskew6 : ( 23 - 16 + 1 );
+ ro_bf_t wr2deskew7 : ( 31 - 24 + 1 );
+} phy_wr_deskew_con7_t;
+
+typedef struct {
+ ro_bf_t wr2deskew8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_wr_deskew_con8_t;
+
+typedef struct {
+ ro_bf_t wr3deskew0 : ( 7 - 0 + 1 );
+ ro_bf_t wr3deskew1 : ( 15 - 8 + 1 );
+ ro_bf_t wr3deskew2 : ( 23 - 16 + 1 );
+ ro_bf_t wr3deskew3 : ( 31 - 24 + 1 );
+} phy_wr_deskew_con9_t;
+
+typedef struct {
+ ro_bf_t wr3deskew4 : ( 7 - 0 + 1 );
+ ro_bf_t wr3deskew5 : ( 15 - 8 + 1 );
+ ro_bf_t wr3deskew6 : ( 23 - 16 + 1 );
+ ro_bf_t wr3deskew7 : ( 31 - 24 + 1 );
+} phy_wr_deskew_con10_t;
+
+typedef struct {
+ ro_bf_t wr3deskew8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_wr_deskew_con11_t;
+
+typedef struct {
+ ro_bf_t wr4deskew0 : ( 7 - 0 + 1 );
+ ro_bf_t wr4deskew1 : ( 15 - 8 + 1 );
+ ro_bf_t wr4deskew2 : ( 23 - 16 + 1 );
+ ro_bf_t wr4deskew3 : ( 31 - 24 + 1 );
+} phy_wr_deskew_con12_t;
+
+typedef struct {
+ ro_bf_t wr4deskew4 : ( 7 - 0 + 1 );
+ ro_bf_t wr4deskew5 : ( 15 - 8 + 1 );
+ ro_bf_t wr4deskew6 : ( 23 - 16 + 1 );
+ ro_bf_t wr4deskew7 : ( 31 - 24 + 1 );
+} phy_wr_deskew_con13_t;
+
+typedef struct {
+ ro_bf_t wr4deskew8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_wr_deskew_con14_t;
+
+typedef struct {
+ ro_bf_t wr5deskew0 : ( 7 - 0 + 1 );
+ ro_bf_t wr5deskew1 : ( 15 - 8 + 1 );
+ ro_bf_t wr5deskew2 : ( 23 - 16 + 1 );
+ ro_bf_t wr5deskew3 : ( 31 - 24 + 1 );
+} phy_wr_deskew_con15_t;
+
+typedef struct {
+ ro_bf_t wr5deskew4 : ( 7 - 0 + 1 );
+ ro_bf_t wr5deskew5 : ( 15 - 8 + 1 );
+ ro_bf_t wr5deskew6 : ( 23 - 16 + 1 );
+ ro_bf_t wr5deskew7 : ( 31 - 24 + 1 );
+} phy_wr_deskew_con16_t;
+
+typedef struct {
+ ro_bf_t wr5deskew8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_wr_deskew_con17_t;
+
+typedef struct {
+ ro_bf_t wr6deskew0 : ( 7 - 0 + 1 );
+ ro_bf_t wr6deskew1 : ( 15 - 8 + 1 );
+ ro_bf_t wr6deskew2 : ( 23 - 16 + 1 );
+ ro_bf_t wr6deskew3 : ( 31 - 24 + 1 );
+} phy_wr_deskew_con18_t;
+
+typedef struct {
+ ro_bf_t wr6deskew4 : ( 7 - 0 + 1 );
+ ro_bf_t wr6deskew5 : ( 15 - 8 + 1 );
+ ro_bf_t wr6deskew6 : ( 23 - 16 + 1 );
+ ro_bf_t wr6deskew7 : ( 31 - 24 + 1 );
+} phy_wr_deskew_con19_t;
+
+typedef struct {
+ ro_bf_t wr6deskew8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_wr_deskew_con20_t;
+
+typedef struct {
+ ro_bf_t wr7deskew0 : ( 7 - 0 + 1 );
+ ro_bf_t wr7deskew1 : ( 15 - 8 + 1 );
+ ro_bf_t wr7deskew2 : ( 23 - 16 + 1 );
+ ro_bf_t wr7deskew3 : ( 31 - 24 + 1 );
+} phy_wr_deskew_con21_t;
+
+typedef struct {
+ ro_bf_t wr7deskew4 : ( 7 - 0 + 1 );
+ ro_bf_t wr7deskew5 : ( 15 - 8 + 1 );
+ ro_bf_t wr7deskew6 : ( 23 - 16 + 1 );
+ ro_bf_t wr7deskew7 : ( 31 - 24 + 1 );
+} phy_wr_deskew_con22_t;
+
+typedef struct {
+ ro_bf_t wr7deskew8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_wr_deskew_con23_t;
+
+typedef struct {
+ ro_bf_t dmdeskew0 : ( 7 - 0 + 1 );
+ ro_bf_t dmdeskew1 : ( 15 - 8 + 1 );
+ ro_bf_t dmdeskew2 : ( 23 - 16 + 1 );
+ ro_bf_t dmdeskew3 : ( 31 - 24 + 1 );
+} phy_dm_deskew_con0_t;
+
+typedef struct {
+ ro_bf_t dmdeskew4 : ( 7 - 0 + 1 );
+ ro_bf_t dmdeskew5 : ( 15 - 8 + 1 );
+ ro_bf_t dmdeskew6 : ( 23 - 16 + 1 );
+ ro_bf_t dmdeskew7 : ( 31 - 24 + 1 );
+} phy_dm_deskew_con1_t;
+
+typedef struct {
+ ro_bf_t dmdeskew8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_dm_deskew_con2_t;
+
+typedef struct {
+ ro_bf_t d0_vwmc0 : ( 7 - 0 + 1 );
+ ro_bf_t d0_vwmc1 : ( 15 - 8 + 1 );
+ ro_bf_t d0_vwmc2 : ( 23 - 16 + 1 );
+ ro_bf_t d0_vwmc3 : ( 31 - 24 + 1 );
+} phy_vwmc_stat0_t;
+
+typedef struct {
+ ro_bf_t d0_vwmc4 : ( 7 - 0 + 1 );
+ ro_bf_t d0_vwmc5 : ( 15 - 8 + 1 );
+ ro_bf_t d0_vwmc6 : ( 23 - 16 + 1 );
+ ro_bf_t d0_vwmc7 : ( 31 - 24 + 1 );
+} phy_vwmc_stat1_t;
+
+typedef struct {
+ ro_bf_t d0_vwmc8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwmc_stat2_t;
+
+typedef struct {
+ ro_bf_t d1_vwmc0 : ( 7 - 0 + 1 );
+ ro_bf_t d1_vwmc1 : ( 15 - 8 + 1 );
+ ro_bf_t d1_vwmc2 : ( 23 - 16 + 1 );
+ ro_bf_t d1_vwmc3 : ( 31 - 24 + 1 );
+} phy_vwmc_stat3_t;
+
+typedef struct {
+ ro_bf_t d1_vwmc4 : ( 7 - 0 + 1 );
+ ro_bf_t d1_vwmc5 : ( 15 - 8 + 1 );
+ ro_bf_t d1_vwmc6 : ( 23 - 16 + 1 );
+ ro_bf_t d1_vwmc7 : ( 31 - 24 + 1 );
+} phy_vwmc_stat4_t;
+
+typedef struct {
+ ro_bf_t d1_vwmc8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwmc_stat5_t;
+
+typedef struct {
+ ro_bf_t d2_vwmc0 : ( 7 - 0 + 1 );
+ ro_bf_t d2_vwmc1 : ( 15 - 8 + 1 );
+ ro_bf_t d2_vwmc2 : ( 23 - 16 + 1 );
+ ro_bf_t d2_vwmc3 : ( 31 - 24 + 1 );
+} phy_vwmc_stat6_t;
+
+typedef struct {
+ ro_bf_t d2_vwmc4 : ( 7 - 0 + 1 );
+ ro_bf_t d2_vwmc5 : ( 15 - 8 + 1 );
+ ro_bf_t d2_vwmc6 : ( 23 - 16 + 1 );
+ ro_bf_t d2_vwmc7 : ( 31 - 24 + 1 );
+} phy_vwmc_stat7_t;
+
+typedef struct {
+ ro_bf_t d2_vwmc8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwmc_stat8_t;
+
+typedef struct {
+ ro_bf_t d3_vwmc4 : ( 7 - 0 + 1 );
+ ro_bf_t d3_vwmc5 : ( 15 - 8 + 1 );
+ ro_bf_t d3_vwmc6 : ( 23 - 16 + 1 );
+ ro_bf_t d3_vwmc7 : ( 31 - 24 + 1 );
+} phy_vwmc_stat9_t;
+
+typedef struct {
+ ro_bf_t d3_vwmc4 : ( 7 - 0 + 1 );
+ ro_bf_t d3_vwmc5 : ( 15 - 8 + 1 );
+ ro_bf_t d3_vwmc6 : ( 23 - 16 + 1 );
+ ro_bf_t d3_vwmc7 : ( 31 - 24 + 1 );
+} phy_vwmc_stat10_t;
+
+typedef struct {
+ ro_bf_t d3_vwmc8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwmc_stat11_t;
+
+typedef struct {
+ ro_bf_t d4_vwmc0 : ( 7 - 0 + 1 );
+ ro_bf_t d4_vwmc1 : ( 15 - 8 + 1 );
+ ro_bf_t d4_vwmc2 : ( 23 - 16 + 1 );
+ ro_bf_t d4_vwmc3 : ( 31 - 24 + 1 );
+} phy_vwmc_stat12_t;
+
+typedef struct {
+ ro_bf_t d4_vwmc4 : ( 7 - 0 + 1 );
+ ro_bf_t d4_vwmc5 : ( 15 - 8 + 1 );
+ ro_bf_t d4_vwmc6 : ( 23 - 16 + 1 );
+ ro_bf_t d4_vwmc7 : ( 31 - 24 + 1 );
+} phy_vwmc_stat13_t;
+
+typedef struct {
+ ro_bf_t d4_vwmc8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwmc_stat14_t;
+
+typedef struct {
+ ro_bf_t d5_vwmc0 : ( 7 - 0 + 1 );
+ ro_bf_t d5_vwmc1 : ( 15 - 8 + 1 );
+ ro_bf_t d5_vwmc2 : ( 23 - 16 + 1 );
+ ro_bf_t d5_vwmc3 : ( 31 - 24 + 1 );
+} phy_vwmc_stat15_t;
+
+typedef struct {
+ ro_bf_t d5_vwmc4 : ( 7 - 0 + 1 );
+ ro_bf_t d5_vwmc5 : ( 15 - 8 + 1 );
+ ro_bf_t d5_vwmc6 : ( 23 - 16 + 1 );
+ ro_bf_t d5_vwmc7 : ( 31 - 24 + 1 );
+} phy_vwmc_stat16_t;
+
+typedef struct {
+ ro_bf_t d5_vwmc8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwmc_stat17_t;
+
+typedef struct {
+ ro_bf_t d6_vwmc0 : ( 7 - 0 + 1 );
+ ro_bf_t d6_vwmc1 : ( 15 - 8 + 1 );
+ ro_bf_t d6_vwmc2 : ( 23 - 16 + 1 );
+ ro_bf_t d6_vwmc3 : ( 31 - 24 + 1 );
+} phy_vwmc_stat18_t;
+
+typedef struct {
+ ro_bf_t d6_vwmc4 : ( 7 - 0 + 1 );
+ ro_bf_t d6_vwmc5 : ( 15 - 8 + 1 );
+ ro_bf_t d6_vwmc6 : ( 23 - 16 + 1 );
+ ro_bf_t d6_vwmc7 : ( 31 - 24 + 1 );
+} phy_vwmc_stat19_t;
+
+typedef struct {
+ ro_bf_t d6_vwmc8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwmc_stat20_t;
+
+typedef struct {
+ ro_bf_t d7_vwmc0 : ( 7 - 0 + 1 );
+ ro_bf_t d7_vwmc1 : ( 15 - 8 + 1 );
+ ro_bf_t d7_vwmc2 : ( 23 - 16 + 1 );
+ ro_bf_t d7_vwmc3 : ( 31 - 24 + 1 );
+} phy_vwmc_stat21_t;
+
+typedef struct {
+ ro_bf_t d7_vwmc4 : ( 7 - 0 + 1 );
+ ro_bf_t d7_vwmc5 : ( 15 - 8 + 1 );
+ ro_bf_t d7_vwmc6 : ( 23 - 16 + 1 );
+ ro_bf_t d7_vwmc7 : ( 31 - 24 + 1 );
+} phy_vwmc_stat22_t;
+
+typedef struct {
+ ro_bf_t d7_vwmc8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwmc_stat23_t;
+
+typedef struct {
+ ro_bf_t dm_vwmc0 : ( 7 - 0 + 1 );
+ ro_bf_t dm_vwmc1 : ( 15 - 8 + 1 );
+ ro_bf_t dm_vwmc2 : ( 23 - 16 + 1 );
+ ro_bf_t dm_vwmc3 : ( 31 - 24 + 1 );
+} phy_dm_vwmc_stat0_t;
+
+typedef struct {
+ ro_bf_t dm_vwmc4 : ( 7 - 0 + 1 );
+ ro_bf_t dm_vwmc5 : ( 15 - 8 + 1 );
+ ro_bf_t dm_vwmc6 : ( 23 - 16 + 1 );
+ ro_bf_t dm_vwmc7 : ( 31 - 24 + 1 );
+} phy_dm_vwmc_stat1_t;
+
+typedef struct {
+ ro_bf_t dm_vwmc8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_dm_vwmc_stat2_t;
+
+typedef struct {
+ ro_bf_t d0_vwml0 : ( 7 - 0 + 1 );
+ ro_bf_t d0_vwml1 : ( 15 - 8 + 1 );
+ ro_bf_t d0_vwml2 : ( 23 - 16 + 1 );
+ ro_bf_t d0_vwml3 : ( 31 - 24 + 1 );
+} phy_vwml_stat0_t;
+
+typedef struct {
+ ro_bf_t d0_vwml4 : ( 7 - 0 + 1 );
+ ro_bf_t d0_vwml5 : ( 15 - 8 + 1 );
+ ro_bf_t d0_vwml6 : ( 23 - 16 + 1 );
+ ro_bf_t d0_vwml7 : ( 31 - 24 + 1 );
+} phy_vwml_stat1_t;
+
+typedef struct {
+ ro_bf_t d0_vwml8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwml_stat2_t;
+
+typedef struct {
+ ro_bf_t d1_vwml0 : ( 7 - 0 + 1 );
+ ro_bf_t d1_vwml1 : ( 15 - 8 + 1 );
+ ro_bf_t d1_vwml2 : ( 23 - 16 + 1 );
+ ro_bf_t d1_vwml3 : ( 31 - 24 + 1 );
+} phy_vwml_stat3_t;
+
+typedef struct {
+ ro_bf_t d1_vwml4 : ( 7 - 0 + 1 );
+ ro_bf_t d1_vwml5 : ( 15 - 8 + 1 );
+ ro_bf_t d1_vwml6 : ( 23 - 16 + 1 );
+ ro_bf_t d1_vwml7 : ( 31 - 24 + 1 );
+} phy_vwml_stat4_t;
+
+typedef struct {
+ ro_bf_t d1_vwml8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwml_stat5_t;
+
+typedef struct {
+ ro_bf_t d2_vwml0 : ( 7 - 0 + 1 );
+ ro_bf_t d2_vwml1 : ( 15 - 8 + 1 );
+ ro_bf_t d2_vwml2 : ( 23 - 16 + 1 );
+ ro_bf_t d2_vwml3 : ( 31 - 24 + 1 );
+} phy_vwml_stat6_t;
+
+typedef struct {
+ ro_bf_t d2_vwml4 : ( 7 - 0 + 1 );
+ ro_bf_t d2_vwml5 : ( 15 - 8 + 1 );
+ ro_bf_t d2_vwml6 : ( 23 - 16 + 1 );
+ ro_bf_t d2_vwml7 : ( 31 - 24 + 1 );
+} phy_vwml_stat7_t;
+
+typedef struct {
+ ro_bf_t d2_vwml8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwml_stat8_t;
+
+typedef struct {
+ ro_bf_t d3_vwml0 : ( 7 - 0 + 1 );
+ ro_bf_t d3_vwml1 : ( 15 - 8 + 1 );
+ ro_bf_t d3_vwml2 : ( 23 - 16 + 1 );
+ ro_bf_t d3_vwml3 : ( 31 - 24 + 1 );
+} phy_vwml_stat9_t;
+
+typedef struct {
+ ro_bf_t d3_vwml4 : ( 7 - 0 + 1 );
+ ro_bf_t d3_vwml5 : ( 15 - 8 + 1 );
+ ro_bf_t d3_vwml6 : ( 23 - 16 + 1 );
+ ro_bf_t d3_vwml7 : ( 31 - 24 + 1 );
+} phy_vwml_stat10_t;
+
+typedef struct {
+ ro_bf_t d3_vwml8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwml_stat11_t;
+
+typedef struct {
+ ro_bf_t d4_vwml0 : ( 7 - 0 + 1 );
+ ro_bf_t d4_vwml1 : ( 15 - 8 + 1 );
+ ro_bf_t d4_vwml2 : ( 23 - 16 + 1 );
+ ro_bf_t d4_vwml3 : ( 31 - 24 + 1 );
+} phy_vwml_stat12_t;
+
+typedef struct {
+ ro_bf_t d4_vwml4 : ( 7 - 0 + 1 );
+ ro_bf_t d4_vwml5 : ( 15 - 8 + 1 );
+ ro_bf_t d4_vwml6 : ( 23 - 16 + 1 );
+ ro_bf_t d4_vwml7 : ( 31 - 24 + 1 );
+} phy_vwml_stat13_t;
+
+typedef struct {
+ ro_bf_t d4_vwml8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwml_stat14_t;
+
+typedef struct {
+ ro_bf_t d5_vwml0 : ( 7 - 0 + 1 );
+ ro_bf_t d5_vwml1 : ( 15 - 8 + 1 );
+ ro_bf_t d5_vwml2 : ( 23 - 16 + 1 );
+ ro_bf_t d5_vwml3 : ( 31 - 24 + 1 );
+} phy_vwml_stat15_t;
+
+typedef struct {
+ ro_bf_t d5_vwml4 : ( 7 - 0 + 1 );
+ ro_bf_t d5_vwml5 : ( 15 - 8 + 1 );
+ ro_bf_t d5_vwml6 : ( 23 - 16 + 1 );
+ ro_bf_t d5_vwml7 : ( 31 - 24 + 1 );
+} phy_vwml_stat16_t;
+
+typedef struct {
+ ro_bf_t d5_vwml8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwml_stat17_t;
+
+typedef struct {
+ ro_bf_t d6_vwml0 : ( 7 - 0 + 1 );
+ ro_bf_t d6_vwml1 : ( 15 - 8 + 1 );
+ ro_bf_t d6_vwml2 : ( 23 - 16 + 1 );
+ ro_bf_t d6_vwml3 : ( 31 - 24 + 1 );
+} phy_vwml_stat18_t;
+
+typedef struct {
+ ro_bf_t d6_vwml4 : ( 7 - 0 + 1 );
+ ro_bf_t d6_vwml5 : ( 15 - 8 + 1 );
+ ro_bf_t d6_vwml6 : ( 23 - 16 + 1 );
+ ro_bf_t d6_vwml7 : ( 31 - 24 + 1 );
+} phy_vwml_stat19_t;
+
+typedef struct {
+ ro_bf_t d6_vwml8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwml_stat20_t;
+
+typedef struct {
+ ro_bf_t d7_vwml0 : ( 7 - 0 + 1 );
+ ro_bf_t d7_vwml1 : ( 15 - 8 + 1 );
+ ro_bf_t d7_vwml2 : ( 23 - 16 + 1 );
+ ro_bf_t d7_vwml3 : ( 31 - 24 + 1 );
+} phy_vwml_stat21_t;
+
+typedef struct {
+ ro_bf_t d7_vwml4 : ( 7 - 0 + 1 );
+ ro_bf_t d7_vwml5 : ( 15 - 8 + 1 );
+ ro_bf_t d7_vwml6 : ( 23 - 16 + 1 );
+ ro_bf_t d7_vwml7 : ( 31 - 24 + 1 );
+} phy_vwml_stat22_t;
+
+typedef struct {
+ ro_bf_t d7_vwml8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwml_stat23_t;
+
+typedef struct {
+ ro_bf_t dm_vwml0 : ( 7 - 0 + 1 );
+ ro_bf_t dm_vwml1 : ( 15 - 8 + 1 );
+ ro_bf_t dm_vwml2 : ( 23 - 16 + 1 );
+ ro_bf_t dm_vwml3 : ( 31 - 24 + 1 );
+} phy_dm_vwml_stat1_t;
+
+typedef struct {
+ ro_bf_t dm_vwml4 : ( 7 - 0 + 1 );
+ ro_bf_t dm_vwml5 : ( 15 - 8 + 1 );
+ ro_bf_t dm_vwml6 : ( 23 - 16 + 1 );
+ ro_bf_t dm_vwml7 : ( 31 - 24 + 1 );
+} phy_dm_vwml_stat2_t;
+
+typedef struct {
+ ro_bf_t dm_vwml8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_dm_vwml_stat3_t;
+
+typedef struct {
+ ro_bf_t d0_vwmr0 : ( 7 - 0 + 1 );
+ ro_bf_t d0_vwmr1 : ( 15 - 8 + 1 );
+ ro_bf_t d0_vwmr2 : ( 23 - 16 + 1 );
+ ro_bf_t d0_vwmr3 : ( 31 - 24 + 1 );
+} phy_vwmr_stat0_t;
+
+typedef struct {
+ ro_bf_t d0_vwmr4 : ( 7 - 0 + 1 );
+ ro_bf_t d0_vwmr5 : ( 15 - 8 + 1 );
+ ro_bf_t d0_vwmr6 : ( 23 - 16 + 1 );
+ ro_bf_t d0_vwmr7 : ( 31 - 24 + 1 );
+} phy_vwmr_stat1_t;
+
+typedef struct {
+ ro_bf_t d0_vwmr8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwmr_stat2_t;
+
+typedef struct {
+ ro_bf_t d1_vwmr0 : ( 7 - 0 + 1 );
+ ro_bf_t d1_vwmr1 : ( 15 - 8 + 1 );
+ ro_bf_t d1_vwmr2 : ( 23 - 16 + 1 );
+ ro_bf_t d1_vwmr3 : ( 31 - 24 + 1 );
+} phy_vwmr_stat3_t;
+
+typedef struct {
+ ro_bf_t d1_vwmr4 : ( 7 - 0 + 1 );
+ ro_bf_t d1_vwmr5 : ( 15 - 8 + 1 );
+ ro_bf_t d1_vwmr6 : ( 23 - 16 + 1 );
+ ro_bf_t d1_vwmr7 : ( 31 - 24 + 1 );
+} phy_vwmr_stat4_t;
+
+typedef struct {
+ ro_bf_t d1_vwmr8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwmr_stat5_t;
+
+typedef struct {
+ ro_bf_t d2_vwmr0 : ( 7 - 0 + 1 );
+ ro_bf_t d2_vwmr1 : ( 15 - 8 + 1 );
+ ro_bf_t d2_vwmr2 : ( 23 - 16 + 1 );
+ ro_bf_t d2_vwmr3 : ( 31 - 24 + 1 );
+} phy_vwmr_stat6_t;
+
+typedef struct {
+ ro_bf_t d2_vwmr4 : ( 7 - 0 + 1 );
+ ro_bf_t d2_vwmr5 : ( 15 - 8 + 1 );
+ ro_bf_t d2_vwmr6 : ( 23 - 16 + 1 );
+ ro_bf_t d2_vwmr7 : ( 31 - 24 + 1 );
+} phy_vwmr_stat7_t;
+
+typedef struct {
+ ro_bf_t d2_vwmr8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwmr_stat8_t;
+
+typedef struct {
+ ro_bf_t d3_vwmr0 : ( 7 - 0 + 1 );
+ ro_bf_t d3_vwmr1 : ( 15 - 8 + 1 );
+ ro_bf_t d3_vwmr2 : ( 23 - 16 + 1 );
+ ro_bf_t d3_vwmr3 : ( 31 - 24 + 1 );
+} phy_vwmr_stat9_t;
+
+typedef struct {
+ ro_bf_t d3_vwmr4 : ( 7 - 0 + 1 );
+ ro_bf_t d3_vwmr5 : ( 15 - 8 + 1 );
+ ro_bf_t d3_vwmr6 : ( 23 - 16 + 1 );
+ ro_bf_t d3_vwmr7 : ( 31 - 24 + 1 );
+} phy_vwmr_stat10_t;
+
+typedef struct {
+ ro_bf_t d3_vwmr8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwmr_stat11_t;
+
+typedef struct {
+ ro_bf_t d4_vwmr0 : ( 7 - 0 + 1 );
+ ro_bf_t d4_vwmr1 : ( 15 - 8 + 1 );
+ ro_bf_t d4_vwmr2 : ( 23 - 16 + 1 );
+ ro_bf_t d4_vwmr3 : ( 31 - 24 + 1 );
+} phy_vwmr_stat12_t;
+
+typedef struct {
+ ro_bf_t d4_vwmr4 : ( 7 - 0 + 1 );
+ ro_bf_t d4_vwmr5 : ( 15 - 8 + 1 );
+ ro_bf_t d4_vwmr6 : ( 23 - 16 + 1 );
+ ro_bf_t d4_vwmr7 : ( 31 - 24 + 1 );
+} phy_vwmr_stat13_t;
+
+typedef struct {
+ ro_bf_t d4_vwmr8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwmr_stat14_t;
+
+typedef struct {
+ ro_bf_t d5_vwmr0 : ( 7 - 0 + 1 );
+ ro_bf_t d5_vwmr1 : ( 15 - 8 + 1 );
+ ro_bf_t d5_vwmr2 : ( 23 - 16 + 1 );
+ ro_bf_t d5_vwmr3 : ( 31 - 24 + 1 );
+} phy_vwmr_stat15_t;
+
+typedef struct {
+ ro_bf_t d5_vwmr4 : ( 7 - 0 + 1 );
+ ro_bf_t d5_vwmr5 : ( 15 - 8 + 1 );
+ ro_bf_t d5_vwmr6 : ( 23 - 16 + 1 );
+ ro_bf_t d5_vwmr7 : ( 31 - 24 + 1 );
+} phy_vwmr_stat16_t;
+
+typedef struct {
+ ro_bf_t d5_vwmr8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwmr_stat17_t;
+
+typedef struct {
+ ro_bf_t d6_vwmr0 : ( 7 - 0 + 1 );
+ ro_bf_t d6_vwmr1 : ( 15 - 8 + 1 );
+ ro_bf_t d6_vwmr2 : ( 23 - 16 + 1 );
+ ro_bf_t d6_vwmr3 : ( 31 - 24 + 1 );
+} phy_vwmr_stat18_t;
+
+typedef struct {
+ ro_bf_t d6_vwmr4 : ( 7 - 0 + 1 );
+ ro_bf_t d6_vwmr5 : ( 15 - 8 + 1 );
+ ro_bf_t d6_vwmr6 : ( 23 - 16 + 1 );
+ ro_bf_t d6_vwmr7 : ( 31 - 24 + 1 );
+} phy_vwmr_stat19_t;
+
+typedef struct {
+ ro_bf_t d6_vwmr8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwmr_stat20_t;
+
+typedef struct {
+ ro_bf_t d7_vwmr0 : ( 7 - 0 + 1 );
+ ro_bf_t d7_vwmr1 : ( 15 - 8 + 1 );
+ ro_bf_t d7_vwmr2 : ( 23 - 16 + 1 );
+ ro_bf_t d7_vwmr3 : ( 31 - 24 + 1 );
+} phy_vwmr_stat21_t;
+
+typedef struct {
+ ro_bf_t d7_vwmr4 : ( 7 - 0 + 1 );
+ ro_bf_t d7_vwmr5 : ( 15 - 8 + 1 );
+ ro_bf_t d7_vwmr6 : ( 23 - 16 + 1 );
+ ro_bf_t d7_vwmr7 : ( 31 - 24 + 1 );
+} phy_vwmr_stat22_t;
+
+typedef struct {
+ ro_bf_t d7_vwmr8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwmr_stat23_t;
+
+typedef struct {
+ ro_bf_t dm_vwmr0 : ( 7 - 0 + 1 );
+ ro_bf_t dm_vwmr1 : ( 15 - 8 + 1 );
+ ro_bf_t dm_vwmr2 : ( 23 - 16 + 1 );
+ ro_bf_t dm_vwmr3 : ( 31 - 24 + 1 );
+} phy_dm_vwmr_stat0_t;
+
+typedef struct {
+ ro_bf_t dm_vwmr4 : ( 7 - 0 + 1 );
+ ro_bf_t dm_vwmr5 : ( 15 - 8 + 1 );
+ ro_bf_t dm_vwmr6 : ( 23 - 16 + 1 );
+ ro_bf_t dm_vwmr7 : ( 31 - 24 + 1 );
+} phy_dm_vwmr_stat1_t;
+
+typedef struct {
+ ro_bf_t dm_vwmr8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_dm_vwmr_stat2_t;
+
+typedef struct {
+ ro_bf_t dq_io_rd0 : ( 7 - 0 + 1 );
+ ro_bf_t dq_io_rd1 : ( 15 - 8 + 1 );
+ ro_bf_t dq_io_rd2 : ( 23 - 16 + 1 );
+ ro_bf_t dq_io_rd3 : ( 31 - 24 + 1 );
+} phy_dq_io_rdata0_t;
+
+typedef struct {
+ ro_bf_t dq_io_rd4 : ( 7 - 0 + 1 );
+ ro_bf_t dq_io_rd5 : ( 15 - 8 + 1 );
+ ro_bf_t dq_io_rd6 : ( 23 - 16 + 1 );
+ ro_bf_t dq_io_rd7 : ( 31 - 24 + 1 );
+} phy_dq_io_rdata1_t;
+
+typedef struct {
+ ro_bf_t dq_io_rd8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_dq_io_rdata2_t;
+
+typedef struct {
+ rw_bf_t version_info : ( 31 - 0 + 1 );
+} phy_version_info_stat0_t;
+
+typedef struct {
+ rw_bf_t zq_auto_en : ( 0 - 0 + 1 );
+ rw_bf_t zq_manual_str : ( 1 - 1 + 1 );
+ rw_bf_t zq_manual_mode : ( 3 - 2 + 1 );
+ rw_bf_t zq_udt_dly : ( 11 - 4 + 1 );
+ rw_bf_t zq_force_impp : ( 14 - 12 + 1 );
+ rw_bf_t zq_force_impn : ( 17 - 15 + 1 );
+ rw_bf_t zq_clk_div_en : ( 18 - 18 + 1 );
+ rw_bf_t zq_mode_noterm : ( 19 - 19 + 1 );
+ rw_bf_t zq_lpddr3 : ( 20 - 20 + 1 );
+ rw_bf_t zq_mode_term : ( 23 - 21 + 1 );
+ rw_bf_t zq_mode_dds : ( 26 - 24 + 1 );
+ rw_bf_t zq_clk_en : ( 27 - 27 + 1 );
+ rw_bf_t zq_mode_pdds : ( 30 - 28 + 1 );
+ rw_bf_t zq_mode_lp4 : ( 31 - 31 + 1 );
+} phy_zq_con0_t;
+
+typedef struct {
+ ro_bf_t zq_done : ( 0 - 0 + 1 );
+ ro_bf_t zq_pending : ( 1 - 1 + 1 );
+ ro_bf_t zq_error : ( 2 - 2 + 1 );
+ ro_bf_t zq_nmon : ( 5 - 3 + 1 );
+ ro_bf_t zq_pmon : ( 8 - 6 + 1 );
+ ro_bf_t reserved_9_15 : ( 15 - 9 + 1 );
+ rw_bf_t zq_vref : ( 21 - 16 + 1 );
+ ro_bf_t reserved_22_31 : ( 31 - 22 + 1 );
+} phy_zq_con1_t;
+
+typedef struct {
+ rw_bf_t ctrl_zq_clk_div : ( 15 - 0 + 1 );
+ rw_bf_t ctrl_zq_timer : ( 31 - 16 + 1 );
+} phy_zq_con2_t;
+
+typedef struct {
+ rw_bf_t zq_ds0_pdds : ( 2 - 0 + 1 );
+ rw_bf_t zq_ds0_dds : ( 5 - 3 + 1 );
+ ro_bf_t reserved_6_7 : ( 7 - 6 + 1 );
+ rw_bf_t zq_ds1_pdds : ( 10 - 8 + 1 );
+ rw_bf_t zq_ds1_dds : ( 13 - 11 + 1 );
+ ro_bf_t reserved_14_15 : ( 15 - 14 + 1 );
+ rw_bf_t zq_ds2_pdds : ( 18 - 16 + 1 );
+ rw_bf_t zq_ds2_dds : ( 21 - 19 + 1 );
+ ro_bf_t reserved_22_23 : ( 23 - 22 + 1 );
+ rw_bf_t zq_ds3_pdds : ( 26 - 24 + 1 );
+ rw_bf_t zq_ds3_dds : ( 29 - 27 + 1 );
+ ro_bf_t reserved_30_31 : ( 31 - 30 + 1 );
+} phy_zq_con3_t;
+
+typedef struct {
+ rw_bf_t zq_ds4_pdds : ( 2 - 0 + 1 );
+ rw_bf_t zq_ds4_dds : ( 5 - 3 + 1 );
+ ro_bf_t reserved_6_7 : ( 7 - 6 + 1 );
+ rw_bf_t zq_ds5_pdds : ( 10 - 8 + 1 );
+ rw_bf_t zq_ds5_dds : ( 13 - 11 + 1 );
+ ro_bf_t reserved_14_15 : ( 15 - 14 + 1 );
+ rw_bf_t zq_ds6_pdds : ( 18 - 16 + 1 );
+ rw_bf_t zq_ds6_dds : ( 21 - 19 + 1 );
+ ro_bf_t reserved_22_23 : ( 23 - 22 + 1 );
+ rw_bf_t zq_ds7_pdds : ( 26 - 24 + 1 );
+ rw_bf_t zq_ds7_dds : ( 29 - 27 + 1 );
+ ro_bf_t reserved_30_31 : ( 31 - 30 + 1 );
+} phy_zq_con4_t;
+
+typedef struct {
+ rw_bf_t zq_ds8_pdds : ( 2 - 0 + 1 );
+ rw_bf_t zq_ds8_dds : ( 5 - 3 + 1 );
+ ro_bf_t reserved_6_31 : ( 31 - 6 + 1 );
+} phy_zq_con5_t;
+
+typedef struct {
+ rw_bf_t zq_ds0_lp4 : ( 0 - 0 + 1 );
+ rw_bf_t zq_ds0_noterm : ( 1 - 1 + 1 );
+ rw_bf_t zq_ds0_rgddr3 : ( 2 - 2 + 1 );
+ rw_bf_t zq_ds0_term : ( 5 - 3 + 1 );
+ ro_bf_t reserved_6_7 : ( 7 - 6 + 1 );
+ rw_bf_t zq_ds1_lp4 : ( 8 - 8 + 1 );
+ rw_bf_t zq_ds1_noterm : ( 9 - 9 + 1 );
+ rw_bf_t zq_ds1_rgddr3 : ( 10 - 10 + 1 );
+ rw_bf_t zq_ds1_term : ( 13 - 11 + 1 );
+ ro_bf_t reserved_14_15 : ( 15 - 14 + 1 );
+ rw_bf_t zq_ds2_lp4 : ( 16 - 16 + 1 );
+ rw_bf_t zq_ds2_noterm : ( 17 - 17 + 1 );
+ rw_bf_t zq_ds2_rgddr3 : ( 18 - 18 + 1 );
+ rw_bf_t zq_ds2_term : ( 21 - 19 + 1 );
+ ro_bf_t reserved_22_23 : ( 23 - 22 + 1 );
+ rw_bf_t zq_ds3_lp4 : ( 24 - 24 + 1 );
+ rw_bf_t zq_ds3_noterm : ( 25 - 25 + 1 );
+ rw_bf_t zq_ds3_rgddr3 : ( 26 - 26 + 1 );
+ rw_bf_t zq_ds3_term : ( 29 - 27 + 1 );
+ ro_bf_t reserved_30_31 : ( 31 - 30 + 1 );
+} phy_zq_con6_t;
+
+typedef struct {
+ rw_bf_t zq_ds4_lp4 : ( 0 - 0 + 1 );
+ rw_bf_t zq_ds4_noterm : ( 1 - 1 + 1 );
+ rw_bf_t zq_ds4_rgddr3 : ( 2 - 2 + 1 );
+ rw_bf_t zq_ds4_term : ( 5 - 3 + 1 );
+ ro_bf_t reserved_6_7 : ( 7 - 6 + 1 );
+ rw_bf_t zq_ds5_lp4 : ( 8 - 8 + 1 );
+ rw_bf_t zq_ds5_noterm : ( 9 - 9 + 1 );
+ rw_bf_t zq_ds5_rgddr3 : ( 10 - 10 + 1 );
+ rw_bf_t zq_ds5_term : ( 13 - 11 + 1 );
+ ro_bf_t reserved_14_15 : ( 15 - 14 + 1 );
+ rw_bf_t zq_ds6_lp4 : ( 16 - 16 + 1 );
+ rw_bf_t zq_ds6_noterm : ( 17 - 17 + 1 );
+ rw_bf_t zq_ds6_rgddr3 : ( 18 - 18 + 1 );
+ rw_bf_t zq_ds6_term : ( 21 - 19 + 1 );
+ ro_bf_t reserved_22_23 : ( 23 - 22 + 1 );
+ rw_bf_t zq_ds7_lp4 : ( 24 - 24 + 1 );
+ rw_bf_t zq_ds7_noterm : ( 25 - 25 + 1 );
+ rw_bf_t zq_ds7_rgddr3 : ( 26 - 26 + 1 );
+ rw_bf_t zq_ds7_term : ( 29 - 27 + 1 );
+ ro_bf_t reserved_30_31 : ( 31 - 30 + 1 );
+} phy_zq_con7_t;
+
+typedef struct {
+ rw_bf_t zq_ds8_lp4 : ( 0 - 0 + 1 );
+ rw_bf_t zq_ds8_noterm : ( 1 - 1 + 1 );
+ rw_bf_t zq_ds8_rgddr3 : ( 2 - 2 + 1 );
+ rw_bf_t zq_ds8_term : ( 5 - 3 + 1 );
+ ro_bf_t reserved_6_31 : ( 31 - 6 + 1 );
+} phy_zq_con8_t;
+
+typedef struct {
+ rw_bf_t zq_ds0_vref : ( 5 - 0 + 1 );
+ rw_bf_t zq_ds0_vref_fsbst : ( 6 - 6 + 1 );
+ rw_bf_t zq_ds0_vref_pd : ( 7 - 7 + 1 );
+ rw_bf_t zq_ds1_vref : ( 13 - 8 + 1 );
+ rw_bf_t zq_ds1_vref_fsbst : ( 14 - 14 + 1 );
+ rw_bf_t zq_ds1_vref_pd : ( 15 - 15 + 1 );
+ rw_bf_t zq_ds2_vref : ( 21 - 16 + 1 );
+ rw_bf_t zq_ds2_vref_fsbst : ( 22 - 22 + 1 );
+ rw_bf_t zq_ds2_vref_pd : ( 23 - 23 + 1 );
+ rw_bf_t zq_ds3_vref : ( 29 - 24 + 1 );
+ rw_bf_t zq_ds3_vref_fsbst : ( 30 - 30 + 1 );
+ rw_bf_t zq_ds3_vref_pd : ( 31 - 31 + 1 );
+} phy_zq_con9_t;
+
+typedef struct {
+ rw_bf_t zq_ds4_vref : ( 5 - 0 + 1 );
+ rw_bf_t zq_ds4_vref_fsbst : ( 6 - 6 + 1 );
+ rw_bf_t zq_ds4_vref_pd : ( 7 - 7 + 1 );
+ rw_bf_t zq_ds5_vref : ( 13 - 8 + 1 );
+ rw_bf_t zq_ds5_vref_fsbst : ( 14 - 14 + 1 );
+ rw_bf_t zq_ds5_vref_pd : ( 15 - 15 + 1 );
+ rw_bf_t zq_ds6_vref : ( 21 - 16 + 1 );
+ rw_bf_t zq_ds6_vref_fsbst : ( 22 - 22 + 1 );
+ rw_bf_t zq_ds6_vref_pd : ( 23 - 23 + 1 );
+ rw_bf_t zq_ds7_vref : ( 29 - 24 + 1 );
+ rw_bf_t zq_ds7_vref_fsbst : ( 30 - 30 + 1 );
+ rw_bf_t zq_ds7_vref_pd : ( 31 - 31 + 1 );
+} phy_zq_con10_t;
+
+typedef struct {
+ rw_bf_t zq_ds8_vref : ( 5 - 0 + 1 );
+ rw_bf_t zq_ds8_vref_fsbst : ( 6 - 6 + 1 );
+ rw_bf_t zq_ds8_vref_pd : ( 7 - 7 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_zq_con11_t;
+
+typedef struct {
+ rw_bf_t zq_ds0_impp : ( 2 - 0 + 1 );
+ rw_bf_t zq_ds0_impn : ( 5 - 3 + 1 );
+ ro_bf_t reserved_6_7 : ( 7 - 6 + 1 );
+ rw_bf_t zq_ds1_impp : ( 10 - 8 + 1 );
+ rw_bf_t zq_ds1_impn : ( 13 - 11 + 1 );
+ ro_bf_t reserved_14_15 : ( 15 - 14 + 1 );
+ rw_bf_t zq_ds2_impp : ( 18 - 16 + 1 );
+ rw_bf_t zq_ds2_impn : ( 21 - 19 + 1 );
+ ro_bf_t reserved_22_23 : ( 23 - 22 + 1 );
+ rw_bf_t zq_ds3_impp : ( 26 - 24 + 1 );
+ rw_bf_t zq_ds3_impn : ( 29 - 27 + 1 );
+ ro_bf_t reserved_30_31 : ( 31 - 30 + 1 );
+} phy_zq_con12_t;
+
+typedef struct {
+ rw_bf_t zq_ds4_impp : ( 2 - 0 + 1 );
+ rw_bf_t zq_ds4_impn : ( 5 - 3 + 1 );
+ ro_bf_t reserved_6_7 : ( 7 - 6 + 1 );
+ rw_bf_t zq_ds5_impp : ( 10 - 8 + 1 );
+ rw_bf_t zq_ds5_impn : ( 13 - 11 + 1 );
+ ro_bf_t reserved_14_15 : ( 15 - 14 + 1 );
+ rw_bf_t zq_ds6_impp : ( 18 - 16 + 1 );
+ rw_bf_t zq_ds6_impn : ( 21 - 19 + 1 );
+ ro_bf_t reserved_22_23 : ( 23 - 22 + 1 );
+ rw_bf_t zq_ds7_impp : ( 26 - 24 + 1 );
+ rw_bf_t zq_ds7_impn : ( 29 - 27 + 1 );
+ ro_bf_t reserved_30_31 : ( 31 - 30 + 1 );
+} phy_zq_con13_t;
+
+typedef struct {
+ rw_bf_t dqs_osc_cnt_init_cs1 : ( 15 - 0 + 1 );
+ rw_bf_t dqs_osc_cnt_init_cs0 : ( 31 - 16 + 1 );
+} phy_dqs_osc_con0_t;
+
+typedef struct {
+ rw_bf_t dqs_osc_cnt_new_cs0 : ( 15 - 0 + 1 );
+ ro_bf_t reserved_16_31 : ( 31 - 16 + 1 );
+} phy_dqs_osc_con1_t;
+
+typedef struct {
+ rw_bf_t dqs_osc_cnt_new_cs1 : ( 15 - 0 + 1 );
+ ro_bf_t reserved_16_31 : ( 31 - 16 + 1 );
+} phy_dqs_osc_con2_t;
+
+typedef struct {
+ rw_bf_t dqs_init_runtime : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_20 : ( 20 - 8 + 1 );
+ ro_bf_t dqs_osc_cnt_applied_cs0 : ( 21 - 21 + 1 );
+ ro_bf_t dqs_osc_cnt_applied_cs1 : ( 22 - 22 + 1 );
+ ro_bf_t dqs_osc_overflow_cs0 : ( 23 - 23 + 1 );
+ ro_bf_t dqs_osc_overflow_cs1 : ( 24 - 24 + 1 );
+ rw_bf_t dqs_upd_range : ( 31 - 25 + 1 );
+} phy_dqs_osc_con3_t;
+
+typedef struct {
+ ro_bf_t offsetw_osc_cs0 : ( 7 - 0 + 1 );
+ ro_bf_t offsetw_osc_cs1 : ( 15 - 8 + 1 );
+ ro_bf_t reserved_16_31 : ( 31 - 16 + 1 );
+} phy_dqs_osc_con4_t;
+
+typedef struct {
+ rw_bf_t cbt_ca_vref : ( 7 - 0 + 1 );
+ rw_bf_t cbt_cmd_ca_vref : ( 8 - 8 + 1 );
+ rw_bf_t cbt_ca_vref_mode_ds_0 : ( 9 - 9 + 1 );
+ rw_bf_t cbt_ca_vref_mode_ds_1 : ( 10 - 10 + 1 );
+ ro_bf_t reserved_11_13 : ( 13 - 11 + 1 );
+ rw_bf_t cbt_cmd_clear : ( 14 - 14 + 1 );
+ rw_bf_t cbt_cmd_ca_vwmr : ( 15 - 15 + 1 );
+ rw_bf_t cbt_cmd_ca_vwml : ( 16 - 16 + 1 );
+ rw_bf_t cbt_cmd_cs_vwmr : ( 17 - 17 + 1 );
+ rw_bf_t cbt_cmd_cs_vwml : ( 18 - 18 + 1 );
+ rw_bf_t cbt_reset : ( 19 - 19 + 1 );
+ rw_bf_t cbt_odt_ca : ( 21 - 20 + 1 );
+ rw_bf_t cbt_cke : ( 23 - 22 + 1 );
+ rw_bf_t cbt_ca_pattern : ( 29 - 24 + 1 );
+ rw_bf_t cbt_cs : ( 31 - 30 + 1 );
+} phy_cbt_con0_t;
+
+
+typedef struct {
+ phy_gnr_con0_t GNR_CON0;
+ phy_cal_con0_t CAL_CON0;
+ phy_cal_con1_t CAL_CON1;
+ phy_cal_con2_t CAL_CON2;
+ phy_cal_con3_t CAL_CON3;
+ phy_wlat_con0_t WLAT_CON0;
+ phy_lp_con0_t LP_CON0;
+ phy_gate_con0_t GATE_CON0;
+ phy_offsetr_con0_t OFFSETR_CON0;
+ phy_offsetr_con1_t OFFSETR_CON1;
+ phy_offsetr_con2_t OFFSETR_CON2;
+ phy_dqlat_con0_t DQLAT_CON0;
+ phy_offsetw_con0_t OFFSETW_CON0;
+ phy_offsetw_con1_t OFFSETW_CON1;
+ phy_offsetw_con2_t OFFSETW_CON2;
+ phy_offset_dq_con0_t OFFSET_DQ_CON0;
+ phy_offsetc_con0_t OFFSETC_CON0;
+ phy_offsetc_con1_t OFFSETC_CON1;
+ phy_offsetc_con2_t OFFSETC_CON2;
+ phy_shiftc_con0_t SHIFTC_CON0;
+ phy_offsetd_con0_t OFFSETD_CON0;
+ ro_bf_t reserved_0x54;
+ phy_offseto_con0_t OFFSETO_CON0;
+ phy_offseto_con1_t OFFSETO_CON1;
+ phy_offseto_con2_t OFFSETO_CON2;
+ ro_bf_t reserved_0x64_0x68[2];
+ phy_wr_lvl_con0_t WR_LVL_CON0;
+ phy_wr_lvl_con1_t WR_LVL_CON1;
+ phy_wr_lvl_con2_t WR_LVL_CON2;
+ phy_wr_lvl_con3_t WR_LVL_CON3;
+ phy_ca_dskew_con0_t CA_DSKEW_CON0;
+ phy_ca_dskew_con1_t CA_DSKEW_CON1;
+ phy_ca_dskew_con2_t CA_DSKEW_CON2;
+ ro_bf_t reserved_0x88_0x90[3];
+ phy_ca_dskew_con4_t CA_DSKEW_CON4;
+ phy_cal_pattern_con0_t CAL_PATTERN_CON0;
+ phy_cal_pattern_con1_t CAL_PATTERN_CON1;
+ phy_cal_pattern_con2_t CAL_PATTERN_CON2;
+ phy_cal_pattern_con3_t CAL_PATTERN_CON3;
+ phy_cal_pattern_con4_t CAL_PATTERN_CON4;
+ phy_cal_pattern_con5_t CAL_PATTERN_CON5;
+ phy_mdll_con0_t MDLL_CON0;
+ phy_mdll_con1_t MDLL_CON1;
+ phy_dvfs_con0_t DVFS_CON0;
+ phy_dvfs_con1_t DVFS_CON1;
+ phy_dvfs_con2_t DVFS_CON2;
+ phy_dvfs_con3_t DVFS_CON3;
+ phy_dvfs_con4_t DVFS_CON4;
+ phy_dvfs_con5_t DVFS_CON5;
+ phy_t_rddata_con0_t T_RDDATA_CON0;
+ phy_t_rddata_con1_t T_RDDATA_CON1;
+ phy_t_rddata_con2_t T_RDDATA_CON2;
+ ro_bf_t reserved_0xDC;
+ phy_cal_fail_stat0_t CAL_FAIL_STAT0;
+ phy_cal_fail_stat1_t CAL_FAIL_STAT1;
+ phy_cal_fail_stat2_t CAL_FAIL_STAT2;
+ phy_cal_fail_stat3_t CAL_FAIL_STAT3;
+ phy_cal_gt_wvmc0_t CAL_GT_WVMC0;
+ phy_cal_gt_wvmc1_t CAL_GT_WVMC1;
+ phy_cal_gt_wvmc2_t CAL_GT_WVMC2;
+ phy_cal_gt_cyc_t CAL_GT_CYC;
+ phy_cal_rd_vwmc0_t CAL_RD_VWMC0;
+ phy_cal_rd_vwmc1_t CAL_RD_VWMC1;
+ phy_cal_rd_vwmc2_t CAL_RD_VWMC2;
+ ro_bf_t reserved_0x10C;
+ phy_cal_rd_vwml0_t CAL_RD_VWML0;
+ phy_cal_rd_vwml1_t CAL_RD_VWML1;
+ phy_cal_rd_vwml2_t CAL_RD_VWML2;
+ ro_bf_t reserved_0x11C;
+ phy_cal_rd_vwmr0_t CAL_RD_VWMR0;
+ phy_cal_rd_vwmr1_t CAL_RD_VWMR1;
+ phy_cal_rd_vwmr2_t CAL_RD_VWMR2;
+ ro_bf_t reserved_0x12C;
+ phy_cal_wr_vwmc0_t CAL_WR_VWMC0;
+ phy_cal_wr_vwmc1_t CAL_WR_VWMC1;
+ phy_cal_wr_vwmc2_t CAL_WR_VWMC2;
+ ro_bf_t reserved_0x13C;
+ phy_cal_wr_vwml0_t CAL_WR_VWML0;
+ phy_cal_wr_vwml1_t CAL_WR_VWML1;
+ phy_cal_wr_vwml2_t CAL_WR_VWML2;
+ ro_bf_t reserved_0x14C;
+ phy_cal_wr_vwmr0_t CAL_WR_VWMR0;
+ phy_cal_wr_vwmr1_t CAL_WR_VWMR1;
+ phy_cal_wr_vwmr2_t CAL_WR_VWMR2;
+ ro_bf_t reserved_0x15C;
+ phy_cal_dm_vwmc0_t CAL_DM_VWMC0;
+ phy_cal_dm_vwmc1_t CAL_DM_VWMC1;
+ phy_cal_dm_vwmc2_t CAL_DM_VWMC2;
+ ro_bf_t reserved_0x16C;
+ phy_cal_dm_vwml0_t CAL_DM_VWML0;
+ phy_cal_dm_vwml1_t CAL_DM_VWML1;
+ phy_cal_dm_vwml2_t CAL_DM_VWML2;
+ ro_bf_t reserved_0x17C;
+ phy_cal_dm_vwmr0_t CAL_DM_VWMR0;
+ phy_cal_dm_vwmr1_t CAL_DM_VWMR1;
+ phy_cal_dm_vwmr2_t CAL_DM_VWMR2;
+ ro_bf_t reserved_0x18C;
+ phy_rd_deskew_con0_t RD_DESKEW_CON0;
+ phy_rd_deskew_con1_t RD_DESKEW_CON1;
+ phy_rd_deskew_con2_t RD_DESKEW_CON2;
+ phy_rd_deskew_con3_t RD_DESKEW_CON3;
+ phy_rd_deskew_con4_t RD_DESKEW_CON4;
+ phy_rd_deskew_con5_t RD_DESKEW_CON5;
+ phy_rd_deskew_con6_t RD_DESKEW_CON6;
+ phy_rd_deskew_con7_t RD_DESKEW_CON7;
+ phy_rd_deskew_con8_t RD_DESKEW_CON8;
+ phy_rd_deskew_con9_t RD_DESKEW_CON9;
+ phy_rd_deskew_con10_t RD_DESKEW_CON10;
+ phy_rd_deskew_con11_t RD_DESKEW_CON11;
+ phy_rd_deskew_con12_t RD_DESKEW_CON12;
+ phy_rd_deskew_con13_t RD_DESKEW_CON13;
+ phy_rd_deskew_con14_t RD_DESKEW_CON14;
+ phy_rd_deskew_con15_t RD_DESKEW_CON15;
+ phy_rd_deskew_con16_t RD_DESKEW_CON16;
+ phy_rd_deskew_con17_t RD_DESKEW_CON17;
+ phy_rd_deskew_con18_t RD_DESKEW_CON18;
+ phy_rd_deskew_con19_t RD_DESKEW_CON19;
+ phy_rd_deskew_con20_t RD_DESKEW_CON20;
+ phy_rd_deskew_con21_t RD_DESKEW_CON21;
+ phy_rd_deskew_con22_t RD_DESKEW_CON22;
+ phy_rd_deskew_con23_t RD_DESKEW_CON23;
+ phy_wr_deskew_con0_t WR_DESKEW_CON0;
+ phy_wr_deskew_con1_t WR_DESKEW_CON1;
+ phy_wr_deskew_con2_t WR_DESKEW_CON2;
+ phy_wr_deskew_con3_t WR_DESKEW_CON3;
+ phy_wr_deskew_con4_t WR_DESKEW_CON4;
+ phy_wr_deskew_con5_t WR_DESKEW_CON5;
+ phy_wr_deskew_con6_t WR_DESKEW_CON6;
+ phy_wr_deskew_con7_t WR_DESKEW_CON7;
+ phy_wr_deskew_con8_t WR_DESKEW_CON8;
+ phy_wr_deskew_con9_t WR_DESKEW_CON9;
+ phy_wr_deskew_con10_t WR_DESKEW_CON10;
+ phy_wr_deskew_con11_t WR_DESKEW_CON11;
+ phy_wr_deskew_con12_t WR_DESKEW_CON12;
+ phy_wr_deskew_con13_t WR_DESKEW_CON13;
+ phy_wr_deskew_con14_t WR_DESKEW_CON14;
+ phy_wr_deskew_con15_t WR_DESKEW_CON15;
+ phy_wr_deskew_con16_t WR_DESKEW_CON16;
+ phy_wr_deskew_con17_t WR_DESKEW_CON17;
+ phy_wr_deskew_con18_t WR_DESKEW_CON18;
+ phy_wr_deskew_con19_t WR_DESKEW_CON19;
+ phy_wr_deskew_con20_t WR_DESKEW_CON20;
+ phy_wr_deskew_con21_t WR_DESKEW_CON21;
+ phy_wr_deskew_con22_t WR_DESKEW_CON22;
+ phy_wr_deskew_con23_t WR_DESKEW_CON23;
+ phy_dm_deskew_con0_t DM_DESKEW_CON0;
+ phy_dm_deskew_con1_t DM_DESKEW_CON1;
+ phy_dm_deskew_con2_t DM_DESKEW_CON2;
+ phy_vwmc_stat0_t VWMC_STAT0;
+ phy_vwmc_stat1_t VWMC_STAT1;
+ phy_vwmc_stat2_t VWMC_STAT2;
+ phy_vwmc_stat3_t VWMC_STAT3;
+ phy_vwmc_stat4_t VWMC_STAT4;
+ phy_vwmc_stat5_t VWMC_STAT5;
+ phy_vwmc_stat6_t VWMC_STAT6;
+ phy_vwmc_stat7_t VWMC_STAT7;
+ phy_vwmc_stat8_t VWMC_STAT8;
+ phy_vwmc_stat9_t VWMC_STAT9;
+ phy_vwmc_stat10_t VWMC_STAT10;
+ phy_vwmc_stat11_t VWMC_STAT11;
+ phy_vwmc_stat12_t VWMC_STAT12;
+ phy_vwmc_stat13_t VWMC_STAT13;
+ phy_vwmc_stat14_t VWMC_STAT14;
+ phy_vwmc_stat15_t VWMC_STAT15;
+ phy_vwmc_stat16_t VWMC_STAT16;
+ phy_vwmc_stat17_t VWMC_STAT17;
+ phy_vwmc_stat18_t VWMC_STAT18;
+ phy_vwmc_stat19_t VWMC_STAT19;
+ phy_vwmc_stat20_t VWMC_STAT20;
+ phy_vwmc_stat21_t VWMC_STAT21;
+ phy_vwmc_stat22_t VWMC_STAT22;
+ phy_vwmc_stat23_t VWMC_STAT23;
+ phy_dm_vwmc_stat0_t DM_VWMC_STAT0;
+ phy_dm_vwmc_stat1_t DM_VWMC_STAT1;
+ phy_dm_vwmc_stat2_t DM_VWMC_STAT2;
+ phy_vwml_stat0_t VWML_STAT0;
+ phy_vwml_stat1_t VWML_STAT1;
+ phy_vwml_stat2_t VWML_STAT2;
+ phy_vwml_stat3_t VWML_STAT3;
+ phy_vwml_stat4_t VWML_STAT4;
+ phy_vwml_stat5_t VWML_STAT5;
+ phy_vwml_stat6_t VWML_STAT6;
+ phy_vwml_stat7_t VWML_STAT7;
+ phy_vwml_stat8_t VWML_STAT8;
+ phy_vwml_stat9_t VWML_STAT9;
+ phy_vwml_stat10_t VWML_STAT10;
+ phy_vwml_stat11_t VWML_STAT11;
+ phy_vwml_stat12_t VWML_STAT12;
+ phy_vwml_stat13_t VWML_STAT13;
+ phy_vwml_stat14_t VWML_STAT14;
+ phy_vwml_stat15_t VWML_STAT15;
+ phy_vwml_stat16_t VWML_STAT16;
+ phy_vwml_stat17_t VWML_STAT17;
+ phy_vwml_stat18_t VWML_STAT18;
+ phy_vwml_stat19_t VWML_STAT19;
+ phy_vwml_stat20_t VWML_STAT20;
+ phy_vwml_stat21_t VWML_STAT21;
+ phy_vwml_stat22_t VWML_STAT22;
+ phy_vwml_stat23_t VWML_STAT23;
+ phy_dm_vwml_stat1_t DM_VWML_STAT1;
+ phy_dm_vwml_stat2_t DM_VWML_STAT2;
+ phy_dm_vwml_stat3_t DM_VWML_STAT3;
+ phy_vwmr_stat0_t VWMR_STAT0;
+ phy_vwmr_stat1_t VWMR_STAT1;
+ phy_vwmr_stat2_t VWMR_STAT2;
+ phy_vwmr_stat3_t VWMR_STAT3;
+ phy_vwmr_stat4_t VWMR_STAT4;
+ phy_vwmr_stat5_t VWMR_STAT5;
+ phy_vwmr_stat6_t VWMR_STAT6;
+ phy_vwmr_stat7_t VWMR_STAT7;
+ phy_vwmr_stat8_t VWMR_STAT8;
+ phy_vwmr_stat9_t VWMR_STAT9;
+ phy_vwmr_stat10_t VWMR_STAT10;
+ phy_vwmr_stat11_t VWMR_STAT11;
+ phy_vwmr_stat12_t VWMR_STAT12;
+ phy_vwmr_stat13_t VWMR_STAT13;
+ phy_vwmr_stat14_t VWMR_STAT14;
+ phy_vwmr_stat15_t VWMR_STAT15;
+ phy_vwmr_stat16_t VWMR_STAT16;
+ phy_vwmr_stat17_t VWMR_STAT17;
+ phy_vwmr_stat18_t VWMR_STAT18;
+ phy_vwmr_stat19_t VWMR_STAT19;
+ phy_vwmr_stat20_t VWMR_STAT20;
+ phy_vwmr_stat21_t VWMR_STAT21;
+ phy_vwmr_stat22_t VWMR_STAT22;
+ phy_vwmr_stat23_t VWMR_STAT23;
+ phy_dm_vwmr_stat0_t DM_VWMR_STAT0;
+ phy_dm_vwmr_stat1_t DM_VWMR_STAT1;
+ phy_dm_vwmr_stat2_t DM_VWMR_STAT2;
+ phy_dq_io_rdata0_t DQ_IO_RDATA0;
+ phy_dq_io_rdata1_t DQ_IO_RDATA1;
+ phy_dq_io_rdata2_t DQ_IO_RDATA2;
+ phy_version_info_stat0_t VERSION_INFO_STAT0;
+ ro_bf_t reserved_0x3B0_0x3C4[6];
+ phy_zq_con0_t ZQ_CON0;
+ phy_zq_con1_t ZQ_CON1;
+ phy_zq_con2_t ZQ_CON2;
+ phy_zq_con3_t ZQ_CON3;
+ phy_zq_con4_t ZQ_CON4;
+ phy_zq_con5_t ZQ_CON5;
+ phy_zq_con6_t ZQ_CON6;
+ phy_zq_con7_t ZQ_CON7;
+ phy_zq_con8_t ZQ_CON8;
+ phy_zq_con9_t ZQ_CON9;
+ phy_zq_con10_t ZQ_CON10;
+ phy_zq_con11_t ZQ_CON11;
+ phy_zq_con12_t ZQ_CON12;
+ phy_zq_con13_t ZQ_CON13;
+ ro_bf_t reserved_0x400_0x5F0[125];
+ phy_dqs_osc_con0_t DQS_OSC_CON0;
+ phy_dqs_osc_con1_t DQS_OSC_CON1;
+ phy_dqs_osc_con2_t DQS_OSC_CON2;
+ phy_dqs_osc_con3_t DQS_OSC_CON3;
+ phy_dqs_osc_con4_t DQS_OSC_CON4;
+ phy_cbt_con0_t CBT_CON0;
+} phy_regs_t;
+
+#endif /* _CPU_SAMSUNG_EXYNOS7_PHY_H_ */
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