[coreboot-gerrit] New patch to review for coreboot: Exynos7: Add clock initialization
Stefan Reinauer (stefan.reinauer@coreboot.org)
gerrit at coreboot.org
Thu May 19 20:38:36 CEST 2016
Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14906
-gerrit
commit 4e882ba09ffc9c55fcc1281186196027935cf8db
Author: Akshay Saraswat <akshay.s at samsung.com>
Date: Thu Aug 7 14:35:41 2014 +0530
Exynos7: Add clock initialization
Adding intial system clock setup for Exynos7 and support for
setting clocks specific to various IPs.
BUG=None
BRANCH=None
TEST=None
Change-Id: Ie1c05820fef1a58b0976bb267f72b790eb341724
Signed-off-by: Akshay Saraswat <akshay.s at samsung.com>
---
src/soc/samsung/exynos7/Makefile.inc | 4 +
src/soc/samsung/exynos7/bootblock.c | 10 +
src/soc/samsung/exynos7/clock.c | 327 ++++++
src/soc/samsung/exynos7/clock_init.c | 1152 ++++++++++++++++++++++
src/soc/samsung/exynos7/include/soc/clock.h | 1043 ++++++++++++++++++++
src/soc/samsung/exynos7/include/soc/clock_init.h | 438 ++++++++
6 files changed, 2974 insertions(+)
diff --git a/src/soc/samsung/exynos7/Makefile.inc b/src/soc/samsung/exynos7/Makefile.inc
index 524407f..920e86a 100644
--- a/src/soc/samsung/exynos7/Makefile.inc
+++ b/src/soc/samsung/exynos7/Makefile.inc
@@ -23,12 +23,16 @@ INCLUDES += -Isrc/soc/samsung/exynos7/include/
# BOOTBLOCK : UART related and minimum required hardware init
bootblock-y += bootblock.c
+bootblock-y += clock.c
+bootblock-y += clock_init.c
bootblock-y += power.c
# ROMSTAGE : Run primitive tests and remaining basic stuff
+romstage-y += clock.c
romstage-y += power.c
# RAMSTAGE : Prepare and load payload
+ramstage-y += clock.c
ramstage-y += cpu.c
ramstage-y += power.c
diff --git a/src/soc/samsung/exynos7/bootblock.c b/src/soc/samsung/exynos7/bootblock.c
index 397d7da..5aa2e55 100644
--- a/src/soc/samsung/exynos7/bootblock.c
+++ b/src/soc/samsung/exynos7/bootblock.c
@@ -22,13 +22,18 @@
#include <bootblock_common.h>
#include <stdlib.h>
+#include <soc/clock.h>
#include <soc/cpu.h>
#include <soc/power.h>
void bootblock_cpu_init(void)
{
+ int is_resume = 0;
+
/* Set PS_HOLD and check reset status */
power_init();
+ if (power_read_reset_status() == EXYNOS7_CHECK_SLEEP)
+ is_resume = 1;
/* SCR_EL3.NS|IRQ|FIQ|EA */
raw_write_scr_el3(raw_read_scr_el3() | 0xf);
@@ -38,4 +43,9 @@ void bootblock_cpu_init(void)
/* Set Counter Frequency */
set_cntfrq(EXYNOS7_COUNTER_FREQ);
+
+ /* Initialize system clocks */
+ if (system_clock_init(is_resume))
+ while(1)
+ ;
}
diff --git a/src/soc/samsung/exynos7/clock.c b/src/soc/samsung/exynos7/clock.c
new file mode 100644
index 0000000..d15bf90
--- /dev/null
+++ b/src/soc/samsung/exynos7/clock.c
@@ -0,0 +1,327 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <assert.h>
+#include <stdlib.h>
+#include <timer.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <soc/clock.h>
+#include <soc/clock_init.h>
+#include <soc/periph.h>
+
+static unsigned long exynos7_get_mmc_clk(int dev_index)
+{
+ struct exynos7_clock_top1 *clk =
+ (struct exynos7_clock_top1 *)EXYNOS7_CMU_TOP1_BASE;
+ unsigned int sel, sel_mmc;
+ unsigned int ratio;
+ unsigned long sclk;
+
+ if (dev_index < 2) {
+ sel = readl(&clk->clk_mux_sel_top1_fsys1);
+ sel_mmc = (sel >> (MMCX_BIT_SHIFT + (1 - dev_index) * 4)) & 0x3;
+ } else {
+ sel = readl(&clk->clk_mux_sel_top1_fsys0);
+ sel_mmc = (sel >> MMCX_BIT_SHIFT) & 0x3;
+ }
+
+ /* get src pll clock */
+ if (sel_mmc == 0) {
+ /* BUS0 has 2 dividor */
+ sclk = get_pll_clk(BUS0_PLL)/2;
+ } else if(sel_mmc == 1) {
+ sclk = get_pll_clk(BUS1_PLL);
+ } else if(sel_mmc == 2) {
+ sclk = get_pll_clk(CCI_PLL);
+ } else if(sel_mmc == 3) {
+ sclk = get_pll_clk(MFC_PLL);
+ } else {
+ printk(BIOS_ERR, "Unsupported mmc mux (%d)\n", sel);
+ return 0;
+ }
+
+ /*
+ * CLK_DIV_TOP1_FSYS0
+ * SCLK_MMC2[25:16]
+ * CLK_DIV_TOP1_FSYS1
+ * SCLK_MMC0[21:12]
+ * SCLK_MMC1[9:0]
+ */
+ if (dev_index < 2) {
+ ratio = readl(&clk->clk_div_top1_fsys1);
+ /* get SCLK_MMCx_RATIO */
+ ratio = (ratio >> (MMCX_BIT_SHIFT + (1 - dev_index) * 4)) & 0xf;
+ } else {
+ ratio = readl(&clk->clk_div_top1_fsys0);
+ /* get SCLK_MMCx_RATIO */
+ ratio = (ratio >> MMCX_BIT_SHIFT) & 0xf;
+ }
+
+ return (sclk / (ratio + 1));
+}
+
+static unsigned long exynos7_get_pll_clk(int pllreg)
+{
+ struct exynos7_clock_ap *clk_ap =
+ (struct exynos7_clock_ap *)EXYNOS7_CMU_AP_BASE;
+ struct exynos7_clock_topc *clk_topc =
+ (struct exynos7_clock_topc *)EXYNOS7_CMU_TOPC_BASE;
+ unsigned long r, m, p, s = 0, fout;
+ unsigned int pll_ratio = 0;
+ unsigned int freq;
+
+ switch (pllreg) {
+ case AP_PLL:
+ r = readl(&clk_ap->pll_con0);
+ break;
+ case BUS0_PLL:
+ r = readl(&clk_topc->bus0_pll_con0);
+ pll_ratio = (readl(&clk_topc->clk_div_topc3) >> 0) & 0x7;
+ break;
+ case BUS1_PLL:
+ r = readl(&clk_topc->bus1_pll_con0);
+ pll_ratio = (readl(&clk_topc->clk_div_topc3) >> 8) & 0x7;
+ break;
+ case CCI_PLL:
+ r = readl(&clk_topc->cci_pll_con0);
+ pll_ratio = (readl(&clk_topc->clk_div_topc3) >> 12) & 0x7;
+ break;
+ case MFC_PLL:
+ r = readl(&clk_topc->mfc_pll_con0);
+ pll_ratio = (readl(&clk_topc->clk_div_topc3) >> 16) & 0x7;
+ break;
+ case MIF_PLL:
+ r = readl(&clk_topc->mif_pll_con0);
+ pll_ratio = (readl(&clk_topc->clk_div_topc3) >> 4) & 0x7;
+ break;
+ default:
+ printk(BIOS_ERR, "Unsupported PLL (%d)\n", pllreg);
+ return 0;
+ }
+
+ /* MIDV [25:16] */
+ m = (r >> 16) & 0x3ff;
+ /* PDIV [13:8] */
+ p = (r >> 8) & 0x3f;
+ /* SDIV [2:0] */
+ s = r & 0x7;
+
+ freq = CONFIG_SYS_CLK_FREQ;
+
+ /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV)) */
+ fout = m * (freq / (p * (1 << s)));
+
+ return (fout / ((unsigned long)pll_ratio + 1));
+}
+
+static unsigned long exynos7_get_pwm_clk(void)
+{
+ struct exynos7_clock_top0 *clk =
+ (struct exynos7_clock_top0 *)EXYNOS7_CMU_TOP0_BASE;
+ unsigned int sel, ratio, pclk;
+
+ /*
+ * CLK_MUX_SEL_TOP03
+ * ACKL_PERIC0_66 [21:20]
+ *
+ * CLK_DIV_TOP03
+ * ACLK_PERIC0_66[25:20]
+ */
+ sel = readl(&clk->clk_mux_sel_top03);
+ ratio = readl(&clk->clk_div_top03);
+
+ sel = (sel >> PWM_BIT_SHIFT) & 0x3;
+ ratio = (ratio >> PWM_BIT_SHIFT) & 0x3f;
+
+ if (sel == 0)
+ pclk = get_pll_clk(BUS0_PLL);
+ else if (sel == 1)
+ pclk = get_pll_clk(BUS1_PLL);
+ else if (sel == 2)
+ pclk = get_pll_clk(CCI_PLL);
+ else if (sel == 3)
+ pclk = get_pll_clk(MFC_PLL);
+ else {
+ printk(BIOS_ERR, "Unsupported pwm mux (%d)\n", sel);
+ return 0;
+ }
+
+ return (pclk / ratio);
+}
+
+static unsigned long exynos7_get_uart_clk(int dev_index)
+{
+ struct exynos7_clock_top0 *clk =
+ (struct exynos7_clock_top0 *)EXYNOS7_CMU_TOP0_BASE;
+ unsigned int sel, ratio, sclk;
+
+ /*
+ * CLK_MUX_SEL_TOP0_PERIC3
+ * - UART0_SEL [17:16], UART1_SEL [13:12]
+ * - UART2_SEL [9:8], UART3_SEL [5:4]
+ *
+ * CLK_DIV_TOP0_PERIC3
+ * - UART0_RATIO [19:16], UART1_RATIO [15:12]
+ * - UART2_RATIO [11:8], UART3_RATIO [7:4]
+ */
+ sel = readl(&clk->clk_mux_sel_top0_peric3);
+ ratio = readl(&clk->clk_div_top0_peric3);
+
+ sel = (sel >> ((4 - dev_index) * 4)) & 0x3;
+ ratio = (ratio >> ((4 - dev_index) * 4)) & 0xf;
+
+ if (sel == 0)
+ sclk = get_pll_clk(BUS0_PLL);
+ else if (sel == 1)
+ sclk = get_pll_clk(BUS1_PLL);
+ else if (sel == 2)
+ sclk = get_pll_clk(CCI_PLL);
+ else if (sel == 3)
+ sclk = get_pll_clk(MFC_PLL);
+ else {
+ printk(BIOS_ERR, "Unsupported uart mux (%d)\n", sel);
+ return 0;
+ }
+
+ return (sclk / (ratio + 1));
+}
+
+static unsigned long exynos7_get_usbdrd_clk(void)
+{
+ struct exynos7_clock_top1 *clk =
+ (struct exynos7_clock_top1 *)EXYNOS7_CMU_TOP1_BASE;
+ unsigned int ratio;
+ unsigned long sclk;
+
+ sclk = get_pll_clk(BUS0_PLL);
+ ratio = readl(&clk->clk_div_top13);
+ ratio = (ratio >> 28) & 0xf;
+
+ return (sclk / (ratio + 1));
+}
+
+static void exynos7_set_mmc_clk(int dev_index, unsigned int div)
+{
+ struct exynos7_clock_top1 *clk =
+ (struct exynos7_clock_top1 *)EXYNOS7_CMU_TOP1_BASE;
+ unsigned int ratio, addr = 0;
+
+ /*
+ * CLK_DIV_TOP1_FSYS0
+ * SCLK_MMC2[25:16]
+ * CLK_DIV_TOP1_FSYS1
+ * SCLK_MMC0[21:12]
+ * SCLK_MMC1[9:0]
+ */
+ if (dev_index < 2) {
+ /*
+ * TODO: can't read this register without cating.
+ * Need to check with AP team why is this casting required.
+ */
+ addr = (unsigned int)(uintptr_t)&clk->clk_div_top1_fsys1;
+ ratio = readl((void *)(uintptr_t)addr);
+ /* clear SCLK_MMCx_RATIO */
+ ratio &= ~(0xf << (MMCX_BIT_SHIFT + (1 - dev_index) * 4));
+ /* set SCLK_MMCx_RATIO */
+ ratio |= ((div & 0xf) << (MMCX_BIT_SHIFT + (1 - dev_index) * 4));
+ } else {
+ addr = (unsigned int)(uintptr_t)&clk->clk_div_top1_fsys0;
+ ratio = readl((void *)(uintptr_t)addr);
+ /* clear SCLK_MMCx_RATIO */
+ ratio &= ~(0xf << MMCX_BIT_SHIFT);
+ /* set SCLK_MMCx_RATIO */
+ ratio |= ((div & 0xf) << MMCX_BIT_SHIFT);
+ }
+
+ writel(ratio, (void *)(uintptr_t)addr);
+}
+
+/* Return ARM clock frequency */
+unsigned long get_arm_clk(void)
+{
+ return 0;
+}
+
+/* Return I2C clock frequency */
+unsigned long get_i2c_clk(void)
+{
+ return exynos7_get_pwm_clk();
+}
+
+/* Return MMC clock frequency */
+unsigned long get_mmc_clk(int dev_index)
+{
+ return exynos7_get_mmc_clk(dev_index);
+}
+
+/* Return PLL clock frequency */
+unsigned long get_pll_clk(int pllreg)
+{
+ return exynos7_get_pll_clk(pllreg);
+}
+
+/* Return PWM clock frequency */
+unsigned long get_pwm_clk(void)
+{
+ return exynos7_get_pwm_clk();
+}
+
+/* Return uart clock frequency */
+unsigned long get_uart_clk(int dev_index)
+{
+ return exynos7_get_uart_clk(dev_index);
+}
+
+/* Return USB clock frequency */
+unsigned long get_usbdrd_clk(void)
+{
+ return exynos7_get_usbdrd_clk();
+}
+
+/* Set MMC clock frequency */
+void set_mmc_clk(int dev_index, uint64_t div)
+{
+ exynos7_set_mmc_clk(dev_index, div);
+}
+
+/* Set DMC frequency */
+void dmc_driver_freq(void)
+{
+ unsigned int val;
+
+ val = MIF_ACLK_MIF_PLL_CLK_MUX_SEL(1)
+ | MIF_MIF_PLL_USER_SEL(1)
+ | MIF_SCLK_HPM_MIF_SEL(2)
+ | MIF_PCLK_MIF_SEL(2)
+ | MIF_ACLK_MIF_USER_SEL(1);
+ writel(val, (void *)(uintptr_t)&mif0->clk_mux_sel_mif0);
+ writel(val, (void *)(uintptr_t)&mif1->clk_mux_sel_mif1);
+ writel(val, (void *)(uintptr_t)&mif2->clk_mux_sel_mif2);
+ writel(val, (void *)(uintptr_t)&mif3->clk_mux_sel_mif3);
+
+ val = TOPC5_MIF_ACLK_MIF_PLL_SEL(1)
+ | TOPC5_MIF_PLL_USER_SEL(1)
+ | TOPC5_MIF_ACLK_MIF_USER_SEL(1)
+ | TOPC5_MIF_ACLK_MIF_SEL(1);
+ writel(val, (void *)(uintptr_t)&topc->clk_mux_sel_topc5);
+
+ val = SCLK_BUS_PLL_G3D_RATIO(1);
+ writel(val, (void *)(uintptr_t)&topc->clk_div_topc3);
+}
diff --git a/src/soc/samsung/exynos7/clock_init.c b/src/soc/samsung/exynos7/clock_init.c
new file mode 100644
index 0000000..e5d9e4f
--- /dev/null
+++ b/src/soc/samsung/exynos7/clock_init.c
@@ -0,0 +1,1152 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <delay.h>
+#include <console/console.h>
+#include <soc/clock.h>
+#include <soc/clock_init.h>
+#include <soc/cpu.h>
+
+
+/* contains AP P, M, S values corresponding to different PLLs */
+static struct pll_spec gpll_ap_spec =
+{
+ .pdiv_min = 1,
+ .pdiv_max = 63,
+ .mdiv_min = 64,
+ .mdiv_max = 1023,
+ .sdiv_min = 0,
+ .sdiv_max = 6,
+ .fref_min = 4,
+ .fref_max = 12,
+ .fvco_min = 1600,
+ .fvco_max = 3304,
+ .fout_min = 25,
+ .fout_max = 3304,
+};
+
+static int clk_pll_find_pms(struct pll_spec *pll_spec, struct clk_pll_pms *pll_pms, uint32_t rate);
+
+static int clk_init_cpu(uint32_t ap_pll)
+{
+ uint32_t val, pll, div1, div2;
+
+ writel(CLOCK_DISABLE_BIT, &ap->clk_mux_sel_ap0);
+
+ switch (ap_pll) {
+ case 2400:
+ pll = set_pll(200, 2, 0);
+ div1 = AP_PCLK_DBG_RATIO(7) | AP_ATCLK_RATIO(7)
+ | AP_PCLK_AP_RATIO(7) | AP_ACLK_AP_RATIO(4)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(7) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 2300:
+ pll = set_pll(575, 6, 0);
+ div1 = AP_PCLK_DBG_RATIO(7) | AP_ATCLK_RATIO(7)
+ | AP_PCLK_AP_RATIO(7) | AP_ACLK_AP_RATIO(4)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(7) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 2200:
+ pll = set_pll(275, 3, 0);
+ div1 = AP_PCLK_DBG_RATIO(7) | AP_ATCLK_RATIO(7)
+ | AP_PCLK_AP_RATIO(7) | AP_ACLK_AP_RATIO(4)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(7) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 2100:
+ pll = set_pll(175, 2, 0);
+ div1 = AP_PCLK_DBG_RATIO(7) | AP_ATCLK_RATIO(7)
+ | AP_PCLK_AP_RATIO(7) | AP_ACLK_AP_RATIO(4)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(7) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 2000:
+ pll = set_pll(250, 3, 0);
+ div1 = AP_PCLK_DBG_RATIO(7) | AP_ATCLK_RATIO(7)
+ | AP_PCLK_AP_RATIO(7) | AP_ACLK_AP_RATIO(4)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(7) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 1900:
+ pll = set_pll(475, 6, 0);
+ div1 = AP_PCLK_DBG_RATIO(7) | AP_ATCLK_RATIO(7)
+ | AP_PCLK_AP_RATIO(7) | AP_ACLK_AP_RATIO(4)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(7) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 1800:
+ pll = set_pll(150, 2, 0);
+ div1 = AP_PCLK_DBG_RATIO(7) | AP_ATCLK_RATIO(7)
+ | AP_PCLK_AP_RATIO(7) | AP_ACLK_AP_RATIO(3)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(7) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 1700:
+ pll = set_pll(425, 6, 0);
+ div1 = AP_PCLK_DBG_RATIO(7) | AP_ATCLK_RATIO(7)
+ | AP_PCLK_AP_RATIO(7) | AP_ACLK_AP_RATIO(3)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(7) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 1600:
+ pll = set_pll(200, 3, 0);
+ div1 = AP_PCLK_DBG_RATIO(7) | AP_ATCLK_RATIO(7)
+ | AP_PCLK_AP_RATIO(7) | AP_ACLK_AP_RATIO(3)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(7) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 1500:
+ pll = set_pll(250, 2, 1);
+ div1 = AP_PCLK_DBG_RATIO(7) | AP_ATCLK_RATIO(7)
+ | AP_PCLK_AP_RATIO(7) | AP_ACLK_AP_RATIO(3)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(7) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 1400:
+ pll = set_pll(350, 3, 1);
+ div1 = AP_PCLK_DBG_RATIO(7) | AP_ATCLK_RATIO(7)
+ | AP_PCLK_AP_RATIO(7) | AP_ACLK_AP_RATIO(3)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(7) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 1300:
+ pll = set_pll(325, 3, 1);
+ div1 = AP_PCLK_DBG_RATIO(7) | AP_ATCLK_RATIO(7)
+ | AP_PCLK_AP_RATIO(7) | AP_ACLK_AP_RATIO(3)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(7) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 1200:
+ pll = set_pll(200, 2, 1);
+ div1 = AP_PCLK_DBG_RATIO(7) | AP_ATCLK_RATIO(7)
+ | AP_PCLK_AP_RATIO(7) | AP_ACLK_AP_RATIO(2)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(7) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 1100:
+ pll = set_pll(275, 3, 1);
+ div1 = AP_PCLK_DBG_RATIO(7) | AP_ATCLK_RATIO(7)
+ | AP_PCLK_AP_RATIO(7) | AP_ACLK_AP_RATIO(2)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(7) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 1000:
+ pll = set_pll(250, 3, 1);
+ div1 = AP_PCLK_DBG_RATIO(6) | AP_ATCLK_RATIO(6)
+ | AP_PCLK_AP_RATIO(6) | AP_ACLK_AP_RATIO(2)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(6) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 900:
+ pll = set_pll(150, 2, 1);
+ div1 = AP_PCLK_DBG_RATIO(6) | AP_ATCLK_RATIO(6)
+ | AP_PCLK_AP_RATIO(6) | AP_ACLK_AP_RATIO(2)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(6) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 800:
+ pll = set_pll(200, 3, 1);
+ div1 = AP_PCLK_DBG_RATIO(5) | AP_ATCLK_RATIO(5)
+ | AP_PCLK_AP_RATIO(5) | AP_ACLK_AP_RATIO(2)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(5) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 700:
+ pll = set_pll(350, 3, 2);
+ div1 = AP_PCLK_DBG_RATIO(5) | AP_ATCLK_RATIO(5)
+ | AP_PCLK_AP_RATIO(5) | AP_ACLK_AP_RATIO(2)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(5) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 600:
+ pll = set_pll(200, 2, 2);
+ div1 = AP_PCLK_DBG_RATIO(4) | AP_ATCLK_RATIO(4)
+ | AP_PCLK_AP_RATIO(4) | AP_ACLK_AP_RATIO(2)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(4) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 500:
+ pll = set_pll(250, 3, 2);
+ div1 = AP_PCLK_DBG_RATIO(3) | AP_ATCLK_RATIO(3)
+ | AP_PCLK_AP_RATIO(3) | AP_ACLK_AP_RATIO(2)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(3) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 400:
+ pll = set_pll(200, 3, 2);
+ div1 = AP_PCLK_DBG_RATIO(3) | AP_ATCLK_RATIO(3)
+ | AP_PCLK_AP_RATIO(3) | AP_ACLK_AP_RATIO(2)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(3) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 300:
+ pll = set_pll(200, 2, 3);
+ div1 = AP_PCLK_DBG_RATIO(3) | AP_ATCLK_RATIO(3)
+ | AP_PCLK_AP_RATIO(3) | AP_ACLK_AP_RATIO(2)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(3) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 200:
+ pll = set_pll(200, 3, 3);
+ div1 = AP_PCLK_DBG_RATIO(3) | AP_ATCLK_RATIO(3)
+ | AP_PCLK_AP_RATIO(3) | AP_ACLK_AP_RATIO(2)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(3) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 100:
+ pll = set_pll(200, 3, 4);
+ div1 = AP_PCLK_DBG_RATIO(3) | AP_ATCLK_RATIO(3)
+ | AP_PCLK_AP_RATIO(3) | AP_ACLK_AP_RATIO(2)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(3) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ default:
+ return -1;
+ }
+
+ if((ap_pll % 100) != 0) {
+ struct clk_pll_pms pll_pms;
+ if(clk_pll_find_pms(&gpll_ap_spec, &pll_pms, ap_pll) < 0) {
+ return -1;
+ }
+
+ pll = set_pll(pll_pms.mdiv, pll_pms.pdiv, pll_pms.sdiv);
+ }
+
+ val = ((pll >> 8) & 0x3F) * 150;
+ writel(val, &ap->pll_lock);
+
+ pll = pll | ENABLE(1) | ENABLE_SDIV_CLKSTOP(0)
+ | ENABLE_MDIV_CLKSTOP(1);
+ writel(pll, &ap->pll_con0);
+ do
+ {
+ val = readl(&ap->pll_con0);
+ } while ((val >> 29) == 0);
+
+ writel(div1, &ap->clk_div_ap0);
+
+ writel(div2, &ap->clk_div_ap1);
+
+ val = AP_BUS_PLL_USER_SEL(1);
+ writel(val, &ap->clk_mux_sel_ap1);
+
+ val = AP_SEL(0);
+ writel(val, &ap->clk_mux_sel_ap2);
+
+ val = AP_PLL_SEL(1);
+ writel(val, &ap->clk_mux_sel_ap0);
+
+ return 0;
+}
+
+static void clk_init_aud(void)
+{
+ uint32_t val;
+
+ val = AUD_PCLK_DBG_AUD_RATIO(2)
+ | AUD_ACLK_AUD_RATIO(1)
+ | AUD_CA5_RATIO(1);
+ writel(val, &aud->clk_div_aud0);
+
+ val = AUD_CDCLK_RATIO(1)
+ | AUD_SCLK_SLIMBUS_RATIO(19)
+ | AUD_SCLK_UART_RATIO(1)
+ | AUD_SCLK_PCM_RATIO(49)
+ | AUD_SCLK_I2S_RATIO(9);
+ writel(val, &aud->clk_div_aud1);
+
+ val = AUD_PLL_USER_SEL(1)
+ | AUD_SCLK_PCM_SEL(0)
+ | AUD_SCLK_I2S_SEL(0);
+ writel(val, &aud->clk_mux_sel_aud);
+}
+
+static void clk_init_bus0(void)
+{
+ uint32_t val;
+
+ val = PCLK_BUS0_133_RATIO(3);
+ writel(val, &bus0->clk_div_bus0);
+ val = ACLK_BUS0_532_USER_SEL(1);
+ writel(val, &bus0->clk_mux_sel_bus0);
+}
+
+static void clk_init_bus1(void)
+{
+ uint32_t val;
+
+ val = PCLK_BUS1_133_RATIO(3);
+ writel(val, &bus1->clk_div_bus1);
+ val = ACLK_BUS1_200_USER_SEL(1) | ACLK_BUS1_532_USER_SEL(1);
+ writel(val, &bus1->clk_mux_sel_bus1);
+}
+
+static void clk_init_ccore(void)
+{
+ uint32_t val;
+
+ val = ACLK_CCORE_266_RATIO(1);
+ writel(val, &ccore->clk_div_ccore);
+ val = ACLK_CCORE_133_USER_SEL(1) | ACLK_CCORE_532_USER_SEL(1);
+ writel(val, &ccore->clk_mux_sel_ccore);
+}
+
+static void clk_init_disp(void)
+{
+ uint32_t val, bits;
+
+ writel(CLOCK_DISABLE_BIT, &disp->clk_mux_sel_disp0);
+
+ bits = set_pll(192, 6, 3);
+ val = ((bits >> 8) & 0x3F) * 150;
+ writel(val, &disp->disp_pll_lock);
+
+ bits = bits | ENABLE(1) | ENABLE_SDIV_CLKSTOP(0)
+ | ENABLE_MDIV_CLKSTOP(1);
+ writel(bits, &disp->disp_pll_con0);
+ val = 0;
+ writel(val, &disp->disp_pll_con1);
+ do
+ {
+ val = readl(&disp->disp_pll_con0);
+ } while ((val >> 29) == 0);
+
+ val = DISP_PCLK_DISP_RATIO(2);
+ writel(val, &disp->clk_div_disp);
+
+ val = DISP0_PLL_SEL(1)
+ | DISP0_ACLK_DISP_400_USER_SEL(1);
+ writel(val, &disp->clk_mux_sel_disp0);
+
+ val = DISP1_SCLK_DECON_INT_ECLK(1)
+ | DISP1_SCLK_DECON_EXT_ECLK(1)
+ | DISP1_SCLK_DECON_VCLK(1)
+ | DISP1_SCLK_DSD(1);
+ writel(val, &disp->clk_mux_sel_disp1);
+
+ val = DISP2_PHYCLK_HDMIPHY_PIXEL_CLKO(1)
+ | DISP2_PHYCLK_HDMIPHY_TMDS_CLKO(1)
+ | DISP2_PHYCLK_MIPIDPHY0_RXCLKESC0(1)
+ | DISP2_PHYCLK_MIPIDPHY0_BITCLKDIV8(1)
+ | DISP2_PHYCLK_MIPIDPHY1_RXCLKESC0(1)
+ | DISP2_PHYCLK_MIPIDPHY1_BITCLKDIV8(1);
+ writel(val, &disp->clk_mux_sel_disp2);
+
+ val = DISP3_SCLK_DECON_INT_ECLK(1)
+ | DISP3_SCLK_DECON_EXT_ECLK(1)
+ | DISP3_SCLK_DECON_INT_EXTCLKPLL(1)
+ | DISP3_SCLK_DECON_EXT_EXTCLKPLL(1);
+ writel(val, &disp->clk_mux_sel_disp3);
+}
+
+/* FSYS0 is Retention Block. No need to reconfigure */
+static void clk_init_fsys0(void)
+{
+ uint32_t val, bits;
+
+ writel(CLOCK_DISABLE_BIT, &fsys0->clk_mux_sel_fsys00);
+
+ bits = set_pll(240, 6, 1);
+ val =((bits >> 8) & 0x3F) * 150;
+ writel(val, &fsys0->hsic_pll_lock);
+
+ bits = bits | ENABLE(1) | ENABLE_SDIV_CLKSTOP(0)
+ | ENABLE_MDIV_CLKSTOP(1);
+ writel(bits, &fsys0->hsic_pll_con0);
+ do
+ {
+ val = readl(&fsys0->hsic_pll_con0);
+ } while ((val >> 29) == 0);
+
+
+ val = FSYS0_USB20_RATIO(9)
+ | FSYS0_PCLK_FSYS0_RATIO(0);
+ writel(val, &fsys0->clk_div_fsys0);
+
+ val = FSYS0_HSIC_PLL_SEL(1)
+ | FSYS0_ACLK_FSYS0_200(1)
+ | FSYS0_PHYCLK_SEL0(0)
+ | FSYS0_PHYCLK_SEL1(0);
+ writel(val, &fsys0->clk_mux_sel_fsys00);
+
+ val = FSYS0_SCLK_USBDRD300(1)
+ | FSYS0_SCLK_MMC2(1)
+ | FSYS0_SCLK_UFSUNIPRO11(1)
+ | FSYS0_SCLK_PHY_FSYS0(1);
+ writel(val, &fsys0->clk_mux_sel_fsys01);
+
+ val = FSYS0_PHYCLK_USBDRD300_UDRD30_PHYCLOCK(1)
+ | FSYS0_PHYCLK_USBDRD300_UDRD30_PIPE_PCLK(1)
+ | FSYS0_PHYCLK_USBHOST20_PHY_FREECLK__HSIC1(1)
+ | FSYS0_PHYCLK_USBHOST20_PHY_PHYCLK__HSIC1(1);
+ writel(val, &fsys0->clk_mux_sel_fsys02);
+
+ val = FSYS0_PHYCLK_UFS_TX0_SYMBOL(1)
+ | FSYS0_PHYCLK_UFS_RX0_SYMBOL(1)
+ | FSYS0_PHYCLK_LLI_TX0_SYMBOL(1)
+ | FSYS0_PHYCLK_LLI_RX0_SYMBOL(1)
+ | FSYS0_PHYCLK_PCIE_TX0(1)
+ | FSYS0_PHYCLK_PCIE_RX0(1);
+ writel(val, &fsys0->clk_mux_sel_fsys03);
+}
+
+/* FSYS1 is Retention Block. No need to reconfigure */
+static void clk_init_fsys1(void)
+{
+ uint32_t val;
+
+ val = FSYS1_PCLK_FSYS1_RATIO(0);
+ writel(val, &fsys1->clk_div_fsys1);
+
+ val = FSYS1_ACLK_FSYS1_200(1)
+ | FSYS1_PHYCLK_SEL0(0)
+ | FSYS1_PHYCLK_SEL1(2);
+ writel(val, &fsys1->clk_mux_sel_fsys10);
+
+ val = FSYS1_SCLK_MMC0(1)
+ | FSYS1_SCLK_MMC1(1)
+ | FSYS1_SCLK_UFSUNIPRO20(1)
+ | FSYS1_SCLK_PHY_FSYS1(1)
+ | FSYS1_SCLK_TLX400_WIFI1(1);
+ writel(val, &fsys1->clk_mux_sel_fsys11);
+
+ val = FSYS1_PHYCLK_UFS20_TX0_SYMBOL(1)
+ | FSYS1_PHYCLK_UFS20_RX0_SYMBOL(1)
+ | FSYS1_PHYCLK_UFS20_RX1_SYMBOL(1)
+ | FSYS1_PHYCLK_PCIE_WIFI1_TX0(1)
+ | FSYS1_PHYCLK_PCIE_WIFI1_RX0(1);
+ writel(val, &fsys1->clk_mux_sel_fsys12);
+}
+
+static void clk_init_g2d(void)
+{
+ uint32_t val;
+
+ val = G2D_PCLK_G2D_RATIO(1);
+ writel(val, &g2d->clk_div_g2d);
+
+ val = G2D_ACLK_G2D_266_USER_SEL(1)
+ | G2D_ACLK_G2D_400_USER_SEL(1);
+ writel(val, &g2d->clk_mux_sel_g2d);
+}
+
+static int clk_init_g3d(void)
+{
+ uint32_t val, bits;
+
+ writel(CLOCK_DISABLE_BIT, &g3d->clk_mux_sel_g3d);
+
+ switch (EXYNOS7_G3D_PLL) {
+ case 700:
+ bits = set_pll(175, 6, 0);
+ break;
+ case 652:
+ bits = set_pll(163, 6, 0);
+ break;
+ case 600:
+ bits = set_pll(150, 6, 0);
+ break;
+ case 532:
+ bits = set_pll(133, 6, 0);
+ break;
+ case 480:
+ bits = set_pll(240, 6, 1);
+ break;
+ case 420:
+ bits = set_pll(210, 6, 1);
+ break;
+ case 350:
+ bits = set_pll(175, 6, 1);
+ break;
+ case 260:
+ bits = set_pll(130, 6, 1);
+ break;
+ case 177:
+ bits = set_pll(177, 6, 2);
+ break;
+ case 100:
+ bits = set_pll(200, 6, 3);
+ break;
+ default:
+ return -1;
+ }
+
+ val = ((bits >> 8) & 0x3F) * 150;
+ writel(val, &g3d->g3d_pll_lock);
+
+ bits = bits | ENABLE(1) | ENABLE_SDIV_CLKSTOP(0)
+ | ENABLE_MDIV_CLKSTOP(1);
+ writel(bits, &g3d->g3d_pll_con0);
+ do
+ {
+ val = readl(&g3d->g3d_pll_con0);
+ } while ((val >> 29) == 0);
+
+ val = G3D_SCLK_HPM_G3D_RATIO(1)
+ | G3D_PCLK_G3D_RATIO(4)
+ | G3D_ACLK_G3D_RATIO(0);
+ writel(val, &g3d->clk_div_g3d);
+
+ val = G3D_SEL(0)
+ | G3D_SCLK_BUS_PLL_G3D_USER_SEL(1)
+ | G3D_PLL_SEL(1);
+ writel(val, &g3d->clk_mux_sel_g3d);
+
+ return 0;
+}
+
+static void clk_init_hevc(void)
+{
+ uint32_t val;
+
+ val = HEVC_PCLK_HEVC_RATIO(3);
+ writel(val, &hevc->clk_div_hevc);
+
+ val = HEVC_ACLK_HEVC_532_USER_SEL(1);
+ writel(val, &hevc->clk_mux_sel_hevc);
+}
+
+static void clk_init_imem(void)
+{
+ uint32_t val = ACLK_IMEM_100_USER_SEL(1)
+ | ACLK_IMEM_200_USER_SEL(1)
+ | ACLK_IMEM_266_USER_SEL(1);
+
+ writel(val, &imem->clk_mux_sel_imem);
+}
+
+static void clk_init_mfc(void)
+{
+ uint32_t val;
+
+ val = MFC_PCLK_MFC_PROMISE_RATIO(0)
+ |MFC_PCLK_MFC_RATIO(3);
+ writel(val, &mfc->clk_div_mfc);
+
+ val = MFC_ACLK_MFC_BUS_532_USER_SEL(1)
+ | MFC_ACLK_MFC_532_USER_SEL(1);
+ writel(val, &mfc->clk_mux_sel_mfc);
+}
+
+static int clk_init_mif(uint32_t mif_pll)
+{
+ uint32_t val, pll;
+
+ writel(PAUSE_MIF(1), &mif0->pause_mif0);
+ writel(PAUSE_MIF(1), &mif1->pause_mif1);
+ writel(PAUSE_MIF(1), &mif2->pause_mif2);
+ writel(PAUSE_MIF(1), &mif3->pause_mif3);
+
+ writel(CLOCK_DISABLE_BIT, &topc->clk_mux_sel_topc5);
+
+ switch (mif_pll) {
+ case 3304:
+ pll = set_pll(413, 3,0);
+ break;
+ case 2912:
+ pll = set_pll(364, 3, 0);
+ break;
+ case 2528:
+ pll = set_pll(316, 3, 0);
+ break;
+ case 2136:
+ pll = set_pll(178, 2, 0);
+ break;
+ case 1656:
+ pll = set_pll(207, 3, 0);
+ break;
+ case 1264:
+ pll = set_pll(316, 3, 1);
+ break;
+ case 1068:
+ pll = set_pll(178, 2, 1);
+ break;
+ case 832:
+ pll = set_pll(208, 3, 1);
+ break;
+ case 696:
+ pll = set_pll(348, 3, 2);
+ break;
+ case 552:
+ pll = set_pll(276, 3, 2);
+ break;
+ case 334:
+ pll = set_pll(334, 3, 3);
+ break;
+ default:
+ return -1;
+ }
+
+ val = ((pll >> 8) & 0x3F) * 150;
+ writel(val, &topc->mif_pll_lock);
+
+ pll = pll | ENABLE(1) | ENABLE_SDIV_CLKSTOP(0)
+ | ENABLE_MDIV_CLKSTOP(1);
+ writel(pll, &topc->mif_pll_con0);
+ do
+ {
+ val = readl(&topc->mif_pll_con0);
+ } while ((val >> 29) == 0);
+
+ pll = MIF_SCLK_HPM_MIF_RATIO(1) | MIF_PCLK_MIF_RATIO(4);
+ writel(pll, &mif0->clk_div_mif0);
+ writel(pll, &mif1->clk_div_mif1);
+ writel(pll, &mif2->clk_div_mif2);
+ writel(pll, &mif3->clk_div_mif3);
+
+ /*
+ * Apply F/F setting before pll mux setting to guarautee
+ * post-dividers margine
+ */
+ val = MIF_ACLK_MIF_PLL_CLK_MUX_SEL(0)
+ | MIF_MIF_PLL_USER_SEL(1)
+ | MIF_SCLK_HPM_MIF_SEL(2)
+ | MIF_PCLK_MIF_SEL(2)
+ | MIF_ACLK_MIF_USER_SEL(1);
+ writel(val, &mif0->clk_mux_sel_mif0);
+ writel(val, &mif1->clk_mux_sel_mif1);
+ writel(val, &mif2->clk_mux_sel_mif2);
+ writel(val, &mif3->clk_mux_sel_mif3);
+
+ val = TOPC5_MIF_ACLK_MIF_PLL_SEL(0)
+ | TOPC5_MIF_PLL_USER_SEL(1)
+ | TOPC5_MIF_ACLK_MIF_USER_SEL(1)
+ | TOPC5_MIF_ACLK_MIF_SEL(1)
+ | TOPC5_MIF_PLL_SEL(0);
+ writel(val, &topc->clk_mux_sel_topc5);
+
+ return 0;
+}
+
+static void clk_init_mscl(void)
+{
+ uint32_t val;
+
+ val = MSCL_PCLK_MSCL_RATIO(3);
+ writel(val, &mscl->clk_div_mscl);
+
+ val = MSCL_ACLK_MSCL_532_USER_SEL(1);
+ writel(val, &mscl->clk_mux_sel_mscl);
+}
+
+static void clk_init_peric0(void)
+{
+ writel(PERIC0_SCLK_UART0_USER_SEL(1)
+ | PERIC0_ACLK_PERIC0_66_USER_SEL(1),
+ &peric0->clk_mux_sel_peric0);
+}
+
+static void clk_init_peric1(void)
+{
+ uint32_t val;
+
+ val = PERIC10_ACLK_PERIC1_66_USER_SEL(1);
+ writel(val, &peric1->clk_mux_sel_peric10);
+
+ val = PERIC11_SCLK_UART3_USER_SEL(1)
+ | PERIC11_SCLK_UART2_USER_SEL(1)
+ | PERIC11_SCLK_UART1_USER_SEL(1)
+ | PERIC11_SCLK_SPI4_USER_SEL(1)
+ | PERIC11_SCLK_SPI3_USER_SEL(1)
+ | PERIC11_SCLK_SPI2_USER_SEL(1)
+ | PERIC11_SCLK_SPI1_USER_SEL(1)
+ | PERIC11_SCLK_SPI0_USER_SEL(1);
+ writel(val, &peric1->clk_mux_sel_peric11);
+}
+
+static void clk_init_peris(void)
+{
+ writel(ACLK_PERIS_66_USER_SEL(1),
+ &peris->clk_mux_sel_peris);
+}
+
+static void clk_init_top0(void)
+{
+ uint32_t val;
+
+ val = ACLK_DISP_400(0) | ACLK_PERIC0_66(7) | ACLK_PERIC1_66(7)
+ | ACLK_VPP0_400(0) | ACLK_VPP1_400(0);
+ writel(val, &top0->clk_div_top03);
+
+ val = ACLK_DISP_400(0) | ACLK_PERIC0_66(2) | ACLK_PERIC1_66(2)
+ | ACLK_VPP0_400(0) | ACLK_VPP1_400(0);
+ writel(val, &top0->clk_mux_sel_top03);
+
+ val = ACLK_ISP0_ISP0_590(0) | ACLK_ISP0_TPU_590(0)
+ | ACLK_ISP0_TREX_532(0) | ACLK_ISP1_ISP1_468(1)
+ | ACLK_ISP1_AHB_117(3);
+ writel(val, &top0->clk_div_top04);
+
+ val = ACLK_ISP0_ISP0_590(5) | ACLK_ISP0_TPU_590(0)
+ | ACLK_ISP0_TREX_532(2) | ACLK_ISP1_ISP1_468(5)
+ | ACLK_ISP1_AHB_117(3);
+ writel(val, &top0->clk_mux_sel_top04);
+
+ val = ACLK_CAM0_CSIS0_690(0) | ACLK_CAM0_BNSA_690(0)
+ | ACLK_CAM0_BNSB_690(2) | ACLK_CAM0_BNSD_690(0)
+ | ACLK_CAM0_CSIS1_174(2);
+ writel(val, &top0->clk_div_top05);
+
+ val = ACLK_CAM0_CSIS0_690(6) | ACLK_CAM0_BNSA_690(6)
+ | ACLK_CAM0_BNSB_690(2) | ACLK_CAM0_BNSD_690(6)
+ | ACLK_CAM0_CSIS1_174(2);
+ writel(val, &top0->clk_mux_sel_top05);
+
+ val = ACLK_CAM0_3AA0_690(0) | ACLK_CAM0_3AA1_468(2)
+ | ACLK_CAM0_TREX_532(0) | ACLK_CAM0_NOCP_133(3);
+ writel(val, &top0->clk_div_top06);
+
+ val = ACLK_CAM0_3AA0_690(6) | ACLK_CAM0_3AA1_468(2)
+ | ACLK_CAM0_TREX_532(2) | ACLK_CAM0_NOCP_133(2);
+ writel(val, &top0->clk_mux_sel_top06);
+
+ val = ACLK_CAM1_SCLVRA_491(0) | ACLK_CAM1_ARM_668(0)
+ | ACLK_CAM1_BUSPERI_334(1) | ACLK_CAM1_BNSCSIS_133(3)
+ | ACLK_CAM1_NOCP_133(3) | ACLK_CAM1_TREX_532(0);
+ writel(val, &top0->clk_div_top07);
+
+ val = ACLK_CAM1_SCLVRA_491(0) | ACLK_CAM1_ARM_668(1)
+ | ACLK_CAM1_BUSPERI_334(1) | ACLK_CAM1_BNSCSIS_133(2)
+ | ACLK_CAM1_NOCP_133(2) | ACLK_CAM1_TREX_532(0);
+ writel(val, &top0->clk_mux_sel_top07);
+
+ val = SCLK_DECON_INT_ECLK(0) | SCLK_DECON_EXT_ECLK(0)
+ | SCLK_DECON_VCLK(0) | SCLK_DSD(0) | SCLK_HDMI_SPDIF(15);
+ writel(val, &top0->clk_div_top0_disp);
+ val = SCLK_DECON_INT_ECLK(0) | SCLK_DECON_EXT_ECLK(0)
+ | SCLK_DECON_VCLK(0) | SCLK_DSD(0) | SCLK_HDMI_SPDIF(3);
+ writel(val, &top0->clk_mux_sel_top0_disp);
+
+ val = SCLK_ISP_SPI0(4) | SCLK_ISP_SPI1(4) | SCLK_ISP_UART(3);
+ writel(val, &top0->clk_div_top0_cam10);
+ val = SCLK_ISP_UART(2);
+ writel(val, &top0->clk_mux_sel_top0_cam10);
+
+ val = SCLK_ISP_PWM(15) | SCLK_ISP_MPWM(15) | SCLK_ISP_SENSOR0(15)
+ | SCLK_ISP_SENSOR1(15) | SCLK_ISP_SENSOR2(15);
+ writel(val, &top0->clk_div_top0_cam11);
+
+ writel(CLOCK_DISABLE_BIT, &top0->clk_mux_sel_top0_cam11);
+
+ val = SCLK_I2S1(15) | SCLK_PCM1(15) | SCLK_SPDIF(15);
+ writel(val, &top0->clk_div_top0_peric0);
+
+ val = SCLK_I2S1(1) | SCLK_PCM1(1) | SCLK_SPDIF(3);
+ writel(val, &top0->clk_mux_sel_top0_peric0);
+
+ val = SCLK_SPI0(4) | SCLK_SPI1(4);
+ writel(val, &top0->clk_div_top0_peric1);
+
+ writel(CLOCK_DISABLE_BIT, &top0->clk_mux_sel_top0_peric1);
+
+ val = SCLK_SPI2(4) | SCLK_SPI3(4);
+ writel(val, &top0->clk_div_top0_peric2);
+
+ writel(CLOCK_DISABLE_BIT, &top0->clk_mux_sel_top0_peric2);
+
+ val = SCLK_SPI4(4) | SCLK_UART0(3) | SCLK_UART1(3) | SCLK_UART2(3)
+ | SCLK_UART3(3);
+ writel(val, &top0->clk_div_top0_peric3);
+
+ val = SCLK_SPI4(0) | SCLK_UART0(2) | SCLK_UART1(2) | SCLK_UART2(2)
+ | SCLK_UART3(2);
+ writel(val, &top0->clk_mux_sel_top0_peric3);
+}
+
+static void clk_init_top1(void)
+{
+ uint32_t val;
+
+ val = ACLK_FSYS0_200(3) | ACLK_FSYS1_200(3);
+ writel(val, &top1->clk_div_top13);
+
+ val = ACLK_FSYS0_200(0) | ACLK_FSYS1_200(1);
+ writel(val, &top1->clk_mux_sel_top13);
+
+ val = SCLK_USBDRD300(9) | SCLK_MMC2(15)
+ | SCLK_UFSUNIPRO11(1) | SCLK_PHY_FSYS0(7)
+ | SCLK_PHY_FSYS0_26M(17);
+ writel(val, &top1->clk_div_top1_fsys0);
+
+ val = SCLK_USBDRD300(0) | SCLK_MMC2(0)
+ | SCLK_UFSUNIPRO11(1) | SCLK_PHY_FSYS0(0)
+ | SCLK_PHY_FSYS0_26M(3);
+ writel(val, &top1->clk_mux_sel_top1_fsys0);
+
+ val = SCLK_MMC0(15) | SCLK_MMC1(15) | SCLK_UFSUNIPRO20(1)
+ | SCLK_TLX400_WIFI1(3) | SCLK_PHY_FSYS1(7);
+ writel(val, &top1->clk_div_top1_fsys1);
+
+ val = SCLK_MMC0(0) | SCLK_MMC1(0) | SCLK_UFSUNIPRO20(1)
+ | SCLK_TLX400_WIFI1(0) | SCLK_PHY_FSYS1(0);
+ writel(val, &top1->clk_mux_sel_top1_fsys1);
+
+ val = SCLK_PHY_FSYS1_26M(17);
+ writel(val, &top1->clk_div_top1_fsys11);
+
+ val = SCLK_PHY_FSYS1_26M(3);
+ writel(val, &top1->clk_mux_sel_top1_fsys11);
+}
+
+static int clk_init_topc(void)
+{
+ uint32_t val, bits;
+
+ switch (EXYNOS7_CCI_PLL) {
+ case 532:
+ bits = set_pll(133, 6, 0);
+ break;
+ case 528:
+ bits = set_pll(66, 3, 0);
+ break;
+ default:
+ return -1;
+ }
+
+ val = ((bits >> 8) & 0x3F) * 150;
+ writel(val, &topc->cci_pll_lock);
+ bits = bits | ENABLE(1) | ENABLE_SDIV_CLKSTOP(0)
+ | ENABLE_MDIV_CLKSTOP(1);
+ writel(bits, &topc->cci_pll_con0);
+ do
+ {
+ val = readl(&topc->cci_pll_con0);
+ } while ((val >> 29) == 0);
+
+ switch (EXYNOS7_BUS0_PLL) {
+ case 1600:
+ bits = set_pll(200, 3, 0);
+ break;
+ case 800:
+ bits = set_pll(200, 3, 1);
+ break;
+ default:
+ return -1;
+ }
+
+ val = ((bits >> 8) & 0x3F) * 150;
+ writel(val, &topc->bus0_pll_lock);
+ bits = (bits | ENABLE(1) | ENABLE_SDIV_CLKSTOP(0)
+ | ENABLE_MDIV_CLKSTOP(1));
+ writel(bits, &topc->bus0_pll_con0);
+ do
+ {
+ val = readl(&topc->bus0_pll_con0);
+ } while ((val >> 29) == 0);
+
+
+ bits = set_pll(167, 6, 0);
+ val = ((bits >> 8) & 0x3F) * 150;
+ writel(val, &topc->bus1_pll_lock);
+ bits = (bits | ENABLE(1) | ENABLE_SDIV_CLKSTOP(0)
+ | ENABLE_MDIV_CLKSTOP(1));
+ writel(bits, &topc->bus1_pll_con0);
+ do
+ {
+ val = readl(&topc->bus1_pll_con0);
+ } while ((val >> 29) == 0);
+
+ bits = set_pll(234, 6, 1);
+ val = ((bits >> 8) & 0x3F) * 150;
+ writel(val, &topc->mfc_pll_lock);
+ bits = (bits | ENABLE(1) | ENABLE_SDIV_CLKSTOP(0)
+ | ENABLE_MDIV_CLKSTOP(1));
+ writel(bits, &topc->mfc_pll_con0);
+ do
+ {
+ val = readl(&topc->mfc_pll_con0);
+ } while ((val >> 29) == 0);
+
+ bits = set_pll(20, 1, 0);
+ val = ((bits >> 8) & 0x3F) * 3000;
+ writel(val, &topc->aud_pll_lock);
+ bits = bits | ENABLE(1) | ENABLE_SDIV_CLKSTOP(0)
+ | ENABLE_MDIV_CLKSTOP(1);
+ writel(bits, &topc->aud_pll_con0);
+ /* KDIV */
+ val = 31457;
+ writel(val, &topc->aud_pll_con1);
+ do
+ {
+ val = readl(&topc->aud_pll_con0);
+ } while ((val >> 29) == 0);
+
+ val = ACLK_IMEM_100(3) | ACLK_IMEM_200(3)
+ | ACLK_IMEM_266(1) | ACLK_BUS1_200(1)
+ | ACLK_CCORE_133(4);
+ writel(val, &topc->clk_div_topc0);
+
+ val = ACLK_IMEM_200(1) | ACLK_IMEM_266(2)
+ | ACLK_BUS1_532(2) | ACLK_BUS0_532(3)
+ | ACLK_CCORE_532(2);
+ writel(val, &topc->clk_mux_sel_topc2);
+
+ val = ACLK_PERIS_66(7) | ACLK_G2D_266(1);
+ writel(val, &topc->clk_div_topc1);
+
+ val = ACLK_PERIS_66(2) | ACLK_MSCL_532(2)
+ | ACLK_MFC_BUS_532(2) | ACLK_HEVC_532(2)
+ | ACLK_MFC_532(2) | ACLK_G2D_266(2);
+ writel(val, &topc->clk_mux_sel_topc3);
+
+ writel(SCLK_CMU_APBIF(3), &topc->clk_div_topc2);
+
+ writel(CLOCK_DISABLE_BIT, &topc->clk_mux_sel_topc4);
+
+ val = SCLK_BUS_PLL_G3D_RATIO(1) | SCLK_BUS0_PLL_MIF_RATIO(7);
+ writel(val, &topc->clk_div_topc3);
+
+ return 0;
+}
+
+static int clk_pll_find_pms(struct pll_spec *pll_spec, struct clk_pll_pms *pll_pms, uint32_t rate)
+{
+ uint32_t pdiv, mdiv, sdiv;
+ uint32_t fref, fvco, fout;
+
+ for(pdiv=pll_spec->pdiv_min; pdiv<=pll_spec->pdiv_max; pdiv++) {
+ fref = FIN / pdiv;
+ if((fref < pll_spec->fref_min) || (fref > pll_spec->fref_max)) {
+ continue;
+ }
+
+ for(mdiv=pll_spec->mdiv_min; mdiv<=pll_spec->mdiv_max; mdiv++) {
+ fvco = FIN * mdiv / pdiv;
+ if((fvco < pll_spec->fvco_min) || (fvco > pll_spec->fvco_max)) {
+ continue;
+ }
+
+ for(sdiv=pll_spec->sdiv_min; sdiv<=pll_spec->sdiv_max; sdiv++) {
+ fout = fvco >> sdiv;
+ if((fout >= pll_spec->fout_min) && (fout <= pll_spec->fout_max)) {
+ if(rate == fout) {
+ pll_pms->pdiv = pdiv;
+ pll_pms->mdiv = mdiv;
+ pll_pms->sdiv = sdiv;
+
+ return 0;
+ }
+ }
+ }
+ }
+ }
+
+ return -1;
+}
+
+
+int system_clock_init(int is_resume)
+{
+ uint32_t val, bits;
+
+ writel(CLOCK_DISABLE_BIT, &ap->armclk_stopctrl);
+ writel(CLOCK_DISABLE_BIT, &top0->clk_mux_sel_top00);
+ writel(CLOCK_DISABLE_BIT, &top1->clk_mux_sel_top10);
+
+ /*
+ * Apply F/F setting before pll mux setting to guarautee
+ * post-dividers margin
+ */
+ switch (EXYNOS7_BUS0_PLL) {
+ case 1600:
+ /* 400MHz=1600MHz/4 for TOPC's BUS0_PLL */
+ writel(TOPC0_SCLK_BUS0_PLL_CMUC_SEL(2), &topc->clk_mux_sel_topc0);
+ val = TOPC1_SCLK_BUS_PLL_G3D_SEL(2)
+ | TOPC1_SCLK_BUS0_PLL_OUT_SEL(1)
+ | TOPC1_SCLK_BUS0_PLL_MIF_SEL(1)
+ | TOPC1_SCLK_BUS0_PLL_AP_SEL(1)
+ | TOPC1_AUD_PLL_SEL(1);
+ /* 800MHz=1600MHz/2 for TOP0,1's BUS0_PLL */
+ writel(val, &topc->clk_mux_sel_topc1);
+ break;
+ case 800:
+ /* 400MHz=800MHz/2 for TOPC's BUS0_PLL */
+ writel(TOPC0_SCLK_BUS0_PLL_CMUC_SEL(1), &topc->clk_mux_sel_topc0);
+ val = TOPC1_SCLK_BUS_PLL_G3D_SEL(2);
+ /* 800MHz=800MHz/1 for TOP0,1's BUS0_PLL */
+ writel(val, &topc->clk_mux_sel_topc1);
+ break;
+ default:
+ return -1;
+ }
+
+ /* 400MHz=800MHz/2 for TOP0's BUS0_PLL */
+ writel(TOP01_HALF_BUS0_PLL_USER(1), &top0->clk_mux_sel_top01);
+ /* 800MHz=800MHz/1 for TOP1's BUS0_PLL */
+ writel(CLOCK_DISABLE_BIT, &top1->clk_mux_sel_top11);
+
+ /* CMU_TOPC */
+ if (clk_init_topc())
+ return -1;
+
+ /* CMU_TOP0 */
+ clk_init_top0();
+
+ /* CMU_TOP1 */
+ clk_init_top1();
+
+ /* CMU_CCORE */
+ clk_init_ccore();
+
+ /* CMU_IMEM */
+ clk_init_imem();
+
+ /* CMU_PERIC0 */
+ clk_init_peric0();
+
+ /* CMU_PERIC1 */
+ clk_init_peric1();
+
+ /* CMU_PERIS */
+ clk_init_peris();
+
+ /* CMU_BUS0 */
+ clk_init_bus0();
+
+ /* CMU_BUS1 */
+ clk_init_bus1();
+
+ /* CMU_AP */
+ if (clk_init_cpu(EXYNOS7_AP_PLL))
+ return -1;
+
+ /* CMU_MIF */
+ if (clk_init_mif(EXYNOS7_MIF_PLL))
+ return -1;
+
+ if(!is_resume) { /* Cold Boot */
+
+ /* CMU_G3D */
+ if (clk_init_g3d())
+ return -1;
+
+ /* CMU_DISP */
+ clk_init_disp();
+
+ /* CMU_AUD */
+ clk_init_aud();
+
+ /* CMU_FSYS0 */
+ clk_init_fsys0();
+
+ /* CMU_FSYS1 */
+ clk_init_fsys1();
+
+ /* CMU_G2D */
+ clk_init_g2d();
+
+ /* CMU_MSCL */
+ clk_init_mscl();
+
+ /* CMU_MFC */
+ clk_init_mfc();
+
+ /* CMU_HEVC */
+ clk_init_hevc();
+ }
+
+ switch (EXYNOS7_BUS0_PLL) {
+ case 1600:
+ val = TOPC0_SCLK_MFC_PLL_CMUC_SEL(0)
+ | TOPC0_SCLK_CCI_PLL_CMUC_SEL(0)
+ | TOPC0_SCLK_BUS1_PLL_CMUC_SEL(0)
+ | TOPC0_SCLK_BUS0_PLL_CMUC_SEL(2)
+ | TOPC0_MFC_PLL_SEL(1)
+ | TOPC0_CCI_PLL_SEL(1)
+ | TOPC0_BUS1_PLL_SEL(1)
+ | TOPC0_BUS0_PLL_SEL(1);
+ bits = TOPC1_SCLK_BUS_PLL_G3D_SEL(2)
+ | TOPC1_SCLK_BUS0_PLL_OUT_SEL(1)
+ | TOPC1_SCLK_BUS0_PLL_MIF_SEL(1)
+ | TOPC1_SCLK_BUS0_PLL_AP_SEL(1)
+ | TOPC1_AUD_PLL_SEL(1);
+ break;
+ case 800:
+ val = TOPC0_SCLK_MFC_PLL_CMUC_SEL(0)
+ | TOPC0_SCLK_CCI_PLL_CMUC_SEL(0)
+ | TOPC0_SCLK_BUS1_PLL_CMUC_SEL(0)
+ | TOPC0_SCLK_BUS0_PLL_CMUC_SEL(1)
+ | TOPC0_MFC_PLL_SEL(1)
+ | TOPC0_CCI_PLL_SEL(1)
+ | TOPC0_BUS1_PLL_SEL(1)
+ | TOPC0_BUS0_PLL_SEL(1);
+ bits = TOPC1_SCLK_BUS_PLL_G3D_SEL(2)
+ | TOPC1_SCLK_BUS0_PLL_OUT_SEL(0)
+ | TOPC1_SCLK_BUS0_PLL_MIF_SEL(0)
+ | TOPC1_SCLK_BUS0_PLL_AP_SEL(0)
+ | TOPC1_AUD_PLL_SEL(0);
+ break;
+ default:
+ return -1;
+ }
+
+ writel(val, &topc->clk_mux_sel_topc0);
+ writel(bits, &topc->clk_mux_sel_topc1);
+
+ val = val | TOP00_BUS0_PLL_USER_SEL(1)
+ | TOP00_BUS1_PLL_USER_SEL(1)
+ | TOP00_CCI_PLL_USER_SEL(1)
+ | TOP00_MFC_PLL_USER_SEL(1)
+ | TOP00_AUD_PLL_USER_SEL(1);
+ writel(val, &top0->clk_mux_sel_top00);
+
+ val = TOP01_SCLK_CMU0_APBIF_SEL(0)
+ | TOP01_HALF_BUS0_PLL_USER(1)
+ | TOP01_HALF_BUS1_PLL_USER(0)
+ | TOP01_HALF_CCI_PLL_USER(0)
+ | TOP01_HALF_MFC_PLL_USER(0);
+ writel(val, &top0->clk_mux_sel_top01);
+
+ val = TOP10_BUS0_PLL_USER_SEL(1)
+ | TOP10_BUS1_PLL_USER_SEL(1)
+ | TOP10_CCI_PLL_USER_SEL(1)
+ | TOP10_MFC_PLL_USER_SEL(1);
+ writel(val, &top1->clk_mux_sel_top10);
+
+ writel(CLOCK_DISABLE_BIT, &top1->clk_mux_sel_top11);
+
+ return 0;
+}
diff --git a/src/soc/samsung/exynos7/include/soc/clock.h b/src/soc/samsung/exynos7/include/soc/clock.h
new file mode 100644
index 0000000..9f51f14
--- /dev/null
+++ b/src/soc/samsung/exynos7/include/soc/clock.h
@@ -0,0 +1,1043 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _CPU_SAMSUNG_EXYNOS7_CLOCK_H_
+#define _CPU_SAMSUNG_EXYNOS7_CLOCK_H_
+
+#include <stdint.h>
+
+#include <soc/cpu.h>
+
+enum periph_id;
+
+/* EXYNOS7 PLL */
+enum pll {
+ AP_PLL,
+ MIF_PLL,
+ MFC_PLL,
+ BUS0_PLL,
+ BUS1_PLL,
+ CCI_PLL
+};
+
+#define CLOCK_ENABLE_BIT 0x1
+#define CLOCK_DISABLE_BIT 0x0
+#define MCT_HZ 24000000
+#define CONFIG_SYS_CLK_FREQ 24000000
+#define MMCX_BIT_SHIFT 24
+#define PWM_BIT_SHIFT 20
+
+struct clk_pll_pms {
+ uint32_t pdiv;
+ uint32_t mdiv;
+ uint32_t sdiv;
+};
+
+struct pll_spec {
+ uint32_t pdiv_min;
+ uint32_t pdiv_max;
+ uint32_t mdiv_min;
+ uint32_t mdiv_max;
+ uint32_t sdiv_min;
+ uint32_t sdiv_max;
+ uint32_t fref_min;
+ uint32_t fref_max;
+ uint32_t fvco_min;
+ uint32_t fvco_max;
+ uint32_t fout_min;
+ uint32_t fout_max;
+};
+
+struct exynos7_clock_ap {
+ uint32_t pll_lock;
+ uint8_t res1[0xfc];
+ uint32_t pll_con0;
+ uint32_t pll_con1;
+ uint32_t pll_con2;
+ uint8_t res3[0xf4];
+ uint32_t clk_mux_sel_ap0;
+ uint32_t clk_mux_sel_ap1;
+ uint32_t clk_mux_sel_ap2;
+ uint8_t res4[0xf4];
+ uint32_t clk_mux_enable_ap0;
+ uint32_t clk_mux_enable_ap1;
+ uint32_t clk_mux_enable_ap2;
+ uint8_t res5[0xf4];
+ uint32_t clk_mux_stat_ap0;
+ uint32_t clk_mux_stat_ap1;
+ uint32_t clk_mux_stat_ap2;
+ uint8_t res6[0x1f4];
+ uint32_t clk_div_ap0;
+ uint32_t clk_div_ap1;
+ uint8_t res7[0xf8];
+ uint32_t clk_div_stat_ap0;
+ uint32_t clk_div_stat_ap1;
+ uint8_t res8[0x3f8];
+ uint32_t clk_en_ip_ap0;
+ uint32_t clk_en_ip_ap1;
+ uint8_t res9[0xf8];
+ uint32_t clkout_cmu_ap;
+ uint32_t clkout_cmu_ap_div_stat;
+ uint8_t res10[0x3f8];
+ uint32_t armclk_stopctrl;
+ uint8_t res15[0x1c];
+ uint32_t pwr_ctrl;
+ uint32_t pwr_ctrl2;
+ uint8_t res11[0x58];
+ uint32_t intr_spread_enable;
+ uint32_t intr_spread_use_standbywfi;
+ uint32_t intr_spread_blocking_duration;
+};
+
+static struct exynos7_clock_ap * const ap =
+ (struct exynos7_clock_ap *)EXYNOS7_CMU_AP_BASE;
+
+struct exynos7_clock_aud {
+ uint8_t res1[0x200];
+ uint32_t clk_mux_sel_aud;
+ uint8_t res2[0xfc];
+ uint32_t clk_mux_enable_aud;
+ uint8_t res3[0xfc];
+ uint32_t clk_mux_stat_aud;
+ uint8_t res4[0x1fc];
+ uint32_t clk_div_aud0;
+ uint32_t clk_div_aud1;
+ uint8_t res5[0xf8];
+ uint32_t clk_div_stat_aud0;
+ uint32_t clk_div_stat_aud1;
+ uint8_t res6[0x3f8];
+ uint32_t clk_en_ip_aud;
+ uint8_t res7[0xfc];
+ uint32_t clkout_cmu_aud;
+ uint32_t clkout_cmu_aud_div_stat;
+};
+
+static struct exynos7_clock_aud * const aud =
+ (struct exynos7_clock_aud *)EXYNOS7_CMU_AUD_BASE;
+
+struct exynos7_clock_bus0 {
+ uint8_t res1[0x200];
+ uint32_t clk_mux_sel_bus0;
+ uint8_t res2[0xfc];
+ uint32_t clk_mux_en_bus0;
+ uint8_t res3[0xfc];
+ uint32_t clk_mux_stat_bus0;
+ uint8_t res4[0x1fc];
+ uint32_t clk_div_bus0;
+ uint8_t res5[0xfc];
+ uint32_t clk_div_stat_bus0;
+ uint8_t res6[0x3fc];
+ uint32_t clk_en_ip_bus0;
+ uint8_t res7[0xfc];
+ uint32_t clkout_cmu_bus0;
+ uint32_t clkout_cmu_bus0_div_stat;
+};
+
+static struct exynos7_clock_bus0 * const bus0 =
+ (struct exynos7_clock_bus0 *)EXYNOS7_CMU_BUS0_BASE;
+
+struct exynos7_clock_bus1 {
+ uint8_t res1[0x200];
+ uint32_t clk_mux_sel_bus1;
+ uint8_t res2[0xfc];
+ uint32_t clk_mux_en_bus1;
+ uint8_t res3[0xfc];
+ uint32_t clk_mux_stat_bus1;
+ uint8_t res4[0x1fc];
+ uint32_t clk_div_bus1;
+ uint8_t res5[0xfc];
+ uint32_t clk_div_stat_bus1;
+ uint8_t res6[0x3fc];
+ uint32_t clk_en_ip_bus1;
+ uint8_t res7[0xfc];
+ uint32_t clkout_cmu_bus1;
+ uint32_t clkout_cmu_bus1_div_stat;
+};
+
+static struct exynos7_clock_bus1 * const bus1 =
+ (struct exynos7_clock_bus1 *)EXYNOS7_CMU_BUS1_BASE;
+
+struct exynos7_clock_ccore {
+ uint8_t res1[0x200];
+ uint32_t clk_mux_sel_ccore;
+ uint8_t res2[0xfc];
+ uint32_t clk_mux_en_ccore;
+ uint8_t res3[0xfc];
+ uint32_t clk_mux_stat_ccore;
+ uint8_t res4[0x1fc];
+ uint32_t clk_div_ccore;
+ uint8_t res5[0xfc];
+ uint32_t clk_div_stat_ccore;
+ uint8_t res6[0x3fc];
+ uint32_t clk_en_ip_ccore0;
+ uint32_t clk_en_ip_ccore1;
+ uint32_t clk_en_ip_ccore2;
+ uint8_t res7[0xf4];
+ uint32_t clkout_cmu_ccore;
+ uint32_t clkout_cmu_ccore_div_stat;
+};
+
+static struct exynos7_clock_ccore * const ccore =
+ (struct exynos7_clock_ccore *)EXYNOS7_CMU_CCORE_BASE;
+
+struct exynos7_clock_disp {
+ uint32_t disp_pll_lock;
+ uint32_t dphy_pll_lock;
+ uint8_t res1[0xf8];
+ uint32_t disp_pll_con0;
+ uint32_t disp_pll_con1;
+ uint32_t disp_pll_con2;
+ uint8_t res2[0x4];
+ uint32_t dphy_pll_con0;
+ uint32_t dphy_pll_con1;
+ uint8_t res3[0xe8];
+ uint32_t clk_mux_sel_disp0;
+ uint32_t clk_mux_sel_disp1;
+ uint32_t clk_mux_sel_disp2;
+ uint32_t clk_mux_sel_disp3;
+ uint32_t clk_mux_sel_disp4;
+ uint32_t clk_mux_sel_disp5;
+ uint8_t res4[0xe8];
+ uint32_t clk_mux_enable_disp0;
+ uint32_t clk_mux_enable_disp1;
+ uint32_t clk_mux_enable_disp2;
+ uint32_t clk_mux_enable_disp3;
+ uint32_t clk_mux_enable_disp4;
+ uint8_t res5[0xec];
+ uint32_t clk_mux_stat_disp0;
+ uint32_t clk_mux_stat_disp1;
+ uint32_t clk_mux_stat_disp2;
+ uint32_t clk_mux_stat_disp3;
+ uint32_t clk_mux_stat_disp4;
+ uint8_t res6[0xf4];
+ uint32_t clk_mux_ignore_disp2;
+ uint8_t res7[0x4];
+ uint32_t clk_mux_ignore_disp4;
+ uint8_t res8[0xec];
+ uint32_t clk_div_disp;
+ uint8_t res9[0xfc];
+ uint32_t clk_div_stat_disp;
+ uint8_t res10[0xfc];
+ uint32_t clk_en_aclk_disp;
+ uint32_t clk_en_aclk_disp_secure_smmu_ro_mmu;
+ uint32_t clk_en_aclk_disp_secure_smmu_rw_mmu;
+ uint32_t clk_en_aclk_disp_secure_smmu_ro_sfw;
+ uint32_t clk_en_aclk_disp_secure_smmu_rw_sfw;
+ uint8_t res11[0xec];
+ uint32_t clk_en_pclk_disp;
+ uint32_t clk_en_pclk_disp_secure_smmu_ro_mmu;
+ uint32_t clk_en_pclk_disp_secure_smmu_rw_mmu;
+ uint32_t clk_en_pclk_disp_secure_smmu_ro_sfw;
+ uint32_t clk_en_pclk_disp_secure_smmu_rw_sfw;
+ uint8_t res12[0xf0];
+ uint32_t clkout_en_sclk_disp1;
+ uint32_t clkout_en_sclk_disp2;
+ uint32_t clkout_en_sclk_disp3;
+ uint32_t clkout_en_sclk_disp4;
+ uint8_t res13[0x1ec];
+ uint32_t clkout_cmu_disp;
+ uint32_t clkout_cmu_disp_div_stat;
+};
+
+static struct exynos7_clock_disp * const disp =
+ (struct exynos7_clock_disp *)EXYNOS7_CMU_DISP_BASE;
+
+struct exynos7_clock_fsys0 {
+ uint32_t hsic_pll_lock;
+ uint8_t res1[0xfc];
+ uint32_t hsic_pll_con0;
+ uint32_t hsic_pll_con1;
+ uint8_t res2[0xf8];
+ uint32_t clk_mux_sel_fsys00;
+ uint32_t clk_mux_sel_fsys01;
+ uint32_t clk_mux_sel_fsys02;
+ uint32_t clk_mux_sel_fsys03;
+ uint8_t res3[0xf0];
+ uint32_t clk_mux_en_fsys00;
+ uint32_t clk_mux_en_fsys01;
+ uint32_t clk_mux_en_fsys02;
+ uint32_t clk_mux_en_fsys03;
+ uint8_t res4[0xf0];
+ uint32_t clk_mux_stat_fsys00;
+ uint32_t clk_mux_stat_fsys01;
+ uint32_t clk_mux_stat_fsys02;
+ uint32_t clk_mux_stat_fsys03;
+ uint8_t res5[0xf0];
+ uint32_t clk_mux_ignore_fsys00;
+ uint32_t clk_mux_ignore_fsys01;
+ uint32_t clk_mux_ignore_fsys02;
+ uint32_t clk_mux_ignore_fsys03;
+ uint8_t res6[0xf0];
+ uint32_t clk_div_fsys0;
+ uint8_t res7[0xfc];
+ uint32_t clk_div_stat_fsys0;
+ uint8_t res8[0xfc];
+ uint32_t clk_en_aclk_fsys00;
+ uint32_t clk_en_aclk_fsys01;
+ uint8_t res9[0xf8];
+ uint32_t clk_en_pclk_fsys0;
+ uint8_t res10[0xfc];
+ uint32_t clk_en_sclk_fsys00;
+ uint32_t clk_en_sclk_fsys01;
+ uint32_t clk_en_sclk_fsys02;
+ uint32_t clk_en_sclk_fsys03;
+ uint8_t res11[0x1f0];
+ uint32_t clkout_cmu_fsys0;
+ uint32_t clkout_cmu_fsys0_div_stat;
+};
+
+static struct exynos7_clock_fsys0 * const fsys0 =
+ (struct exynos7_clock_fsys0 *)EXYNOS7_CMU_FSYS0_BASE;
+
+struct exynos7_clock_fsys1 {
+ uint8_t res1[0x200];
+ uint32_t clk_mux_sel_fsys10;
+ uint32_t clk_mux_sel_fsys11;
+ uint32_t clk_mux_sel_fsys12;
+ uint8_t res2[0xf4];
+ uint32_t clk_mux_en_fsys10;
+ uint32_t clk_mux_en_fsys11;
+ uint32_t clk_mux_en_fsys12;
+ uint8_t res3[0xf4];
+ uint32_t clk_mux_stat_fsys10;
+ uint32_t clk_mux_stat_fsys11;
+ uint32_t clk_mux_stat_fsys12;
+ uint8_t res4[0xf4];
+ uint32_t clk_mux_ignore_fsys10;
+ uint32_t clk_mux_ignore_fsys11;
+ uint32_t clk_mux_ignore_fsys12;
+ uint8_t res5[0xf4];
+ uint32_t clk_div_fsys1;
+ uint8_t res6[0xfc];
+ uint32_t clk_div_stat_fsys1;
+ uint8_t res7[0xfc];
+ uint32_t clk_en_aclk_fsys1;
+ uint8_t res8[0xfc];
+ uint32_t clk_en_pclk_fsys1;
+ uint8_t res9[0xfc];
+ uint32_t clk_en_sclk_fsys10;
+ uint32_t clk_en_sclk_fsys11;
+ uint32_t clk_en_sclk_fsys12;
+ uint32_t clk_en_sclk_fsys13;
+ uint8_t res10[0x1f0];
+ uint32_t clkout_cmu_fsys1;
+ uint32_t clkout_cmu_fsys1_div_stat;
+};
+
+static struct exynos7_clock_fsys1 * const fsys1 =
+ (struct exynos7_clock_fsys1 *)EXYNOS7_CMU_FSYS1_BASE;
+
+struct exynos7_clock_g2d {
+ uint8_t res1[0x200];
+ uint32_t clk_mux_sel_g2d;
+ uint8_t res2[0xfc];
+ uint32_t clk_mux_en_g2d;
+ uint8_t res3[0xfc];
+ uint32_t clk_mux_stat_g2d;
+ uint8_t res4[0x1fc];
+ uint32_t clk_div_g2d;
+ uint8_t res5[0xfc];
+ uint32_t clk_div_stat_g2d;
+ uint8_t res6[0xfc];
+ uint32_t clk_en_aclk_g2d;
+ uint8_t res7[0xfc];
+ uint32_t clk_en_pclk_g2d;
+ uint8_t res8[0xfc];
+ uint32_t clk_en_sclk_g2d;
+ uint8_t res9[0x1fc];
+ uint32_t clkout_cmu_g2d;
+ uint32_t clkout_cmu_g2d_div_stat;
+};
+
+static struct exynos7_clock_g2d * const g2d =
+ (struct exynos7_clock_g2d *)EXYNOS7_CMU_G2D_BASE;
+
+struct exynos7_clock_g3d {
+ uint32_t g3d_pll_lock;
+ uint8_t res1[0xfc];
+ uint32_t g3d_pll_con0;
+ uint32_t g3d_pll_con1;
+ uint32_t g3d_pll_con2;
+ uint8_t res2[0xf4];
+ uint32_t clk_mux_sel_g3d;
+ uint8_t res3[0xfc];
+ uint32_t clk_mux_enable_g3d;
+ uint8_t res4[0xfc];
+ uint32_t clk_mux_stat_g3d;
+ uint8_t res5[0x1fc];
+ uint32_t clk_div_g3d;
+ uint8_t res6[0xfc];
+ uint32_t clk_div_stat_g3d;
+ uint8_t res7[0xfc];
+ uint32_t clk_en_aclk_g3d;
+ uint8_t res8[0xfc];
+ uint32_t clk_en_pclk_g3d;
+ uint8_t res9[0xfc];
+ uint32_t clk_en_sclk_g3d;
+ uint8_t res10[0x1fc];
+ uint32_t clkout_cmu_g3d;
+ uint32_t clkout_cmu_g3d_div_stat;
+ uint8_t res11[0x3f8];
+ uint32_t clk_stopctrl;
+};
+
+static struct exynos7_clock_g3d * const g3d =
+ (struct exynos7_clock_g3d *)EXYNOS7_CMU_G3D_BASE;
+
+struct exynos7_clock_hevc {
+ uint8_t res1[0x200];
+ uint32_t clk_mux_sel_hevc;
+ uint8_t res2[0xfc];
+ uint32_t clk_mux_en_hevc;
+ uint8_t res3[0xfc];
+ uint32_t clk_mux_stat_hevc;
+ uint8_t res4[0x1fc];
+ uint32_t clk_div_hevc;
+ uint8_t res5[0xfc];
+ uint32_t clk_div_stat_hevc;
+ uint8_t res6[0xfc];
+ uint32_t clk_en_aclk_hevc;
+ uint8_t res7[0xfc];
+ uint32_t clk_en_pclk_hevc;
+ uint8_t res8[0xfc];
+ uint32_t clk_en_sclk_hevc;
+ uint8_t res9[0x1fc];
+ uint32_t clkout_cmu_hevc;
+ uint32_t clkout_cmu_hevc_div_stat;
+};
+
+static struct exynos7_clock_hevc * const hevc =
+ (struct exynos7_clock_hevc *)EXYNOS7_CMU_HEVC_BASE;
+
+struct exynos7_clock_imem {
+ uint8_t res1[0x200];
+ uint32_t clk_mux_sel_imem;
+ uint8_t res2[0xfc];
+ uint32_t clk_mux_en_imem;
+ uint8_t res3[0xfc];
+ uint32_t clk_mux_stat_imem;
+ uint8_t res4[0x3fc];
+ uint32_t clk_en_aclk_imem0;
+ uint32_t clk_en_aclk_imem1;
+ uint32_t clk_en_aclk_imem_secure_int_mem;
+ uint32_t clk_en_aclk_imem_secure_sss;
+ uint32_t clk_en_aclk_imem_secure_slim_sss;
+ uint32_t clk_en_aclk_imem_secure_rtic;
+ uint32_t clk_en_aclk_imem_secure_sysmmu600_sss;
+ uint32_t clk_en_aclk_imem_secure_sysmmu600_slim_sss;
+ uint32_t clk_en_aclk_imem_secure_cm3_apm;
+ uint32_t clk_en_aclk_imem_secure_ahb_busmatrix_apm;
+ uint32_t clk_en_aclk_imem_secure_isramc_apm;
+ uint32_t clk_en_aclk_imem_secure_ahb2_apb_bridge_apm;
+ uint32_t clk_en_aclk_imem_secure_pdma_imem;
+ uint8_t res5[0xcc];
+ uint32_t clk_en_pclk_imem0;
+ uint32_t clk_en_pclk_imem1;
+ uint32_t clk_en_pclk_imem_secure_int_mem;
+ uint32_t clk_en_pclk_imem_secure_sss;
+ uint32_t clk_en_pclk_imem_secure_slim_sss;
+ uint32_t clk_en_pclk_imem_secure_rtic;
+ uint32_t clk_en_pclk_imem_secure_sysmmu600_sss;
+ uint32_t clk_en_pclk_imem_secure_sysmmu600_slim_sss;
+ uint32_t clk_en_pclk_imem_secure_cm3_apm;
+ uint32_t clk_en_pclk_imem_secure_ahb_busmatrix_apm;
+ uint32_t clk_en_pclk_imem_secure_isramc_apm;
+ uint32_t clk_en_pclk_imem_secure_ahb2_apb_bridge_apm;
+ uint32_t clk_en_pclk_imem_secure_pdma_imem;
+ uint8_t res6[0x2cc];
+ uint32_t clkout_cmu_imem;
+ uint32_t clkout_cmu_imem_div_stat;
+};
+
+static struct exynos7_clock_imem * const imem =
+ (struct exynos7_clock_imem *)EXYNOS7_CMU_IMEM_BASE;
+
+struct exynos7_clock_mfc {
+ uint8_t res1[0x200];
+ uint32_t clk_mux_sel_mfc;
+ uint8_t res2[0xfc];
+ uint32_t clk_mux_en_mfc;
+ uint8_t res3[0xfc];
+ uint32_t clk_mux_stat_mfc;
+ uint8_t res4[0x1fc];
+ uint32_t clk_div_mfc;
+ uint8_t res5[0xfc];
+ uint32_t clk_div_stat_mfc;
+ uint8_t res6[0xfc];
+ uint32_t clk_en_aclk_mfc;
+ uint32_t clk_en_aclk_mfc_secure_smmu_mfc_0;
+ uint32_t clk_en_aclk_mfc_secure_sfw_mfc_0;
+ uint32_t clk_en_aclk_mfc_secure_smmu_mfc_1;
+ uint32_t clk_en_aclk_mfc_secure_sfw_mfc_1;
+ uint8_t res7[0xec];
+ uint32_t clk_en_pclk_mfc;
+ uint32_t clk_en_pclk_mfc_secure_smmu_mfc_0;
+ uint32_t clk_en_pclk_mfc_secure_sfw_mfc_0;
+ uint32_t clk_en_pclk_mfc_secure_smmu_mfc_1;
+ uint32_t clk_en_pclk_mfc_secure_sfw_mfc_1;
+ uint8_t res8[0x2ec];
+ uint32_t clkout_cmu_mfc;
+ uint32_t clkout_cmu_mfc_div_stat;
+};
+
+static struct exynos7_clock_mfc * const mfc =
+ (struct exynos7_clock_mfc *)EXYNOS7_CMU_MFC_BASE;
+
+struct exynos7_clock_mif0 {
+ uint8_t res1[0x200];
+ uint32_t clk_mux_sel_mif0;
+ uint8_t res2[0xfc];
+ uint32_t clk_mux_enable_mif0;
+ uint8_t res3[0xfc];
+ uint32_t clk_mux_stat_mif0;
+ uint8_t res4[0x1fc];
+ uint32_t clk_div_mif0;
+ uint8_t res5[0xfc];
+ uint32_t clk_div_stat_mif0;
+ uint8_t res6[0xfc];
+ uint32_t clk_en_aclk_mif0;
+ uint32_t clk_en_aclk_mif0_secure_drex_tz;
+ uint8_t res7[0xf8];
+ uint32_t clk_en_pclk_mif0;
+ uint32_t clk_en_pclk_mif0_secure_drex_tz;
+ uint8_t res8[0xf8];
+ uint32_t clk_en_sclk_mif0;
+ uint32_t clk_en_sclk_mif0_secure_drex_tz;
+ uint8_t res9[0x1f8];
+ uint32_t clkout_cmu_mif0;
+ uint32_t clkout_cmu_mif0_div_stat;
+ uint8_t res10[0x3f8];
+ uint32_t pause_mif0;
+ uint8_t res11[0x8];
+ uint32_t ddrphy_lock_ctrl_mif0;
+};
+
+static struct exynos7_clock_mif0 * const mif0 =
+ (struct exynos7_clock_mif0 *)EXYNOS7_CMU_MIF0_BASE;
+
+struct exynos7_clock_mif1 {
+ uint8_t res1[0x200];
+ uint32_t clk_mux_sel_mif1;
+ uint8_t res2[0xfc];
+ uint32_t clk_mux_enable_mif1;
+ uint8_t res3[0xfc];
+ uint32_t clk_mux_stat_mif1;
+ uint8_t res4[0x1fc];
+ uint32_t clk_div_mif1;
+ uint8_t res5[0xfc];
+ uint32_t clk_div_stat_mif1;
+ uint8_t res6[0xfc];
+ uint32_t clk_en_aclk_mif1;
+ uint32_t clk_en_aclk_mif1_secure_drex_tz;
+ uint8_t res7[0xf8];
+ uint32_t clk_en_pclk_mif1;
+ uint32_t clk_en_pclk_mif1_secure_drex_tz;
+ uint8_t res8[0xf8];
+ uint32_t clk_en_sclk_mif1;
+ uint32_t clk_en_sclk_mif1_secure_drex_tz;
+ uint8_t res9[0x1f8];
+ uint32_t clkout_cmu_mif1;
+ uint32_t clkout_cmu_mif1_div_stat;
+ uint8_t res10[0x3f8];
+ uint32_t pause_mif1;
+ uint8_t res11[0x8];
+ uint32_t ddrphy_lock_ctrl_mif1;
+};
+
+static struct exynos7_clock_mif1 * const mif1 =
+ (struct exynos7_clock_mif1 *)EXYNOS7_CMU_MIF1_BASE;
+
+struct exynos7_clock_mif2 {
+ uint8_t res1[0x200];
+ uint32_t clk_mux_sel_mif2;
+ uint8_t res2[0xfc];
+ uint32_t clk_mux_enable_mif2;
+ uint8_t res3[0xfc];
+ uint32_t clk_mux_stat_mif2;
+ uint8_t res4[0x1fc];
+ uint32_t clk_div_mif2;
+ uint8_t res5[0xfc];
+ uint32_t clk_div_stat_mif2;
+ uint8_t res6[0xfc];
+ uint32_t clk_en_aclk_mif2;
+ uint32_t clk_en_aclk_mif2_secure_drex_tz;
+ uint8_t res7[0xf8];
+ uint32_t clk_en_pclk_mif2;
+ uint32_t clk_en_pclk_mif2_secure_drex_tz;
+ uint8_t res8[0xf8];
+ uint32_t clk_en_sclk_mif2;
+ uint32_t clk_en_sclk_mif2_secure_drex_tz;
+ uint8_t res9[0x1f8];
+ uint32_t clkout_cmu_mif2;
+ uint32_t clkout_cmu_mif2_div_stat;
+ uint8_t res10[0x3f8];
+ uint32_t pause_mif2;
+ uint8_t res11[0x8];
+ uint32_t ddrphy_lock_ctrl_mif2;
+};
+
+static struct exynos7_clock_mif2 * const mif2 =
+ (struct exynos7_clock_mif2 *)EXYNOS7_CMU_MIF2_BASE;
+
+struct exynos7_clock_mif3 {
+ uint8_t res1[0x200];
+ uint32_t clk_mux_sel_mif3;
+ uint8_t res2[0xfc];
+ uint32_t clk_mux_enable_mif3;
+ uint8_t res3[0xfc];
+ uint32_t clk_mux_stat_mif3;
+ uint8_t res4[0x1fc];
+ uint32_t clk_div_mif3;
+ uint8_t res5[0xfc];
+ uint32_t clk_div_stat_mif3;
+ uint8_t res6[0xfc];
+ uint32_t clk_en_aclk_mif3;
+ uint32_t clk_en_aclk_mif3_secure_drex_tz;
+ uint8_t res7[0xf8];
+ uint32_t clk_en_pclk_mif3;
+ uint32_t clk_en_pclk_mif3_secure_drex_tz;
+ uint8_t res8[0xf8];
+ uint32_t clk_en_sclk_mif3;
+ uint32_t clk_en_sclk_mif3_secure_drex_tz;
+ uint8_t res9[0x1f8];
+ uint32_t clkout_cmu_mif3;
+ uint32_t clkout_cmu_mif3_div_stat;
+ uint8_t res10[0x3f8];
+ uint32_t pause_mif3;
+ uint8_t res11[0x8];
+ uint32_t ddrphy_lock_ctrl_mif3;
+};
+
+static struct exynos7_clock_mif3 * const mif3 =
+ (struct exynos7_clock_mif3 *)EXYNOS7_CMU_MIF3_BASE;
+
+struct exynos7_clock_mscl {
+ uint8_t res1[0x200];
+ uint32_t clk_mux_sel_mscl;
+ uint8_t res2[0xfc];
+ uint32_t clk_mux_en_mscl;
+ uint8_t res3[0xfc];
+ uint32_t clk_mux_stat_mscl;
+ uint8_t res4[0x1fc];
+ uint32_t clk_div_mscl;
+ uint8_t res5[0xfc];
+ uint32_t clk_div_stat_mscl;
+ uint8_t res6[0xfc];
+ uint32_t clk_en_aclk_mscl;
+ uint32_t clk_en_aclk_mscl_secure_smmu_0_mmu;
+ uint32_t clk_en_aclk_mscl_secure_smmu_0_sfw;
+ uint32_t clk_en_aclk_mscl_secure_smmu_1_mmu;
+ uint32_t clk_en_aclk_mscl_secure_smmu_1_sfw;
+ uint32_t clk_en_aclk_mscl_secure_smmu_g2d_mmu;
+ uint32_t clk_en_aclk_mscl_secure_smmu_g2d_sfw;
+ uint8_t res7[0xe4];
+ uint32_t clk_en_pclk_mscl;
+ uint32_t clk_en_pclk_mscl_secure_smmu_0_mmu;
+ uint32_t clk_en_pclk_mscl_secure_smmu_0_sfw;
+ uint32_t clk_en_pclk_mscl_secure_smmu_1_mmu;
+ uint32_t clk_en_pclk_mscl_secure_smmu_1_sfw;
+ uint32_t clk_en_pclk_mscl_secure_smmu_g2d_mmu;
+ uint32_t clk_en_pclk_mscl_secure_smmu_g2d_sfw;
+ uint8_t res8[0xe4];
+ uint32_t clk_en_sclk_mscl;
+ uint8_t res9[0x1fc];
+ uint32_t clkout_cmu_mscl;
+ uint32_t clkout_cmu_mscl_div_stat;
+};
+
+static struct exynos7_clock_mscl * const mscl =
+ (struct exynos7_clock_mscl *)EXYNOS7_CMU_MSCL_BASE;
+
+struct exynos7_clock_peric0 {
+ uint8_t res1[0x200];
+ uint32_t clk_mux_sel_peric0;
+ uint8_t res2[0xfc];
+ uint32_t clk_mux_en_peric0;
+ uint8_t res3[0xfc];
+ uint32_t clk_mux_stat_peric0;
+ uint8_t res4[0x3fc];
+ uint32_t clk_en_aclk_peric0;
+ uint8_t res5[0xfc];
+ uint32_t clk_en_pclk_peric0;
+ uint8_t res6[0xfc];
+ uint32_t clk_en_sclk_peric0;
+ uint8_t res7[0x1fc];
+ uint32_t clkout_cmu_peric0;
+ uint32_t clkout_cmu_peric0_div_stat;
+};
+
+static struct exynos7_clock_peric0 * const peric0 =
+ (struct exynos7_clock_peric0 *)EXYNOS7_CMU_PERIC0_BASE;
+
+struct exynos7_clock_peric1 {
+ uint8_t res1[0x200];
+ uint32_t clk_mux_sel_peric10;
+ uint32_t clk_mux_sel_peric11;
+ uint32_t clk_mux_sel_peric12;
+ uint8_t res2[0xf4];
+ uint32_t clk_mux_en_peric10;
+ uint32_t clk_mux_en_peric11;
+ uint32_t clk_mux_en_peric12;
+ uint8_t res3[0xf4];
+ uint32_t clk_mux_stat_peric10;
+ uint32_t clk_mux_stat_peric11;
+ uint32_t clk_mux_stat_peric12;
+ uint8_t res4[0x3f4];
+ uint32_t clk_en_aclk_peric1;
+ uint8_t res5[0xfc];
+ uint32_t clk_en_pclk_peric1;
+ uint8_t res6[0xfc];
+ uint32_t clk_en_sclk_peric1;
+ uint8_t res7[0x1fc];
+ uint32_t clkout_cmu_peric1;
+ uint32_t clkout_cmu_peric1_div_stat;
+};
+
+static struct exynos7_clock_peric1 * const peric1 =
+ (struct exynos7_clock_peric1 *)EXYNOS7_CMU_PERIC1_BASE;
+
+struct exynos7_clock_peris {
+ uint8_t res1[0x200];
+ uint32_t clk_mux_sel_peris;
+ uint8_t res2[0xfc];
+ uint32_t clk_mux_en_peris;
+ uint8_t res3[0xfc];
+ uint32_t clk_mux_stat_peris;
+ uint8_t res4[0x3fc];
+ uint32_t clk_en_aclk_peris;
+ uint8_t res5[0xfc];
+ uint32_t clk_en_pclk_peris;
+ uint32_t clk_en_pclk_peris_secure_tzpc;
+ uint32_t clk_en_pclk_peris_secure_otp;
+ uint32_t clk_en_pclk_peris_secure_rtc;
+ uint32_t clk_en_pclk_peris_secure_chipid;
+ uint8_t res6[0xec];
+ uint32_t clk_en_sclk_peris;
+ uint32_t clk_en_sclk_peris_secure_tzpc;
+ uint32_t clk_en_sclk_peris_secure_otp;
+ uint32_t clk_en_sclk_peris_secure_rtc;
+ uint32_t clk_en_sclk_peris_secure_chipid;
+ uint8_t res7[0x1ec];
+ uint32_t clkout_cmu_peris;
+ uint32_t clkout_cmu_peris_div_stat;
+};
+
+static struct exynos7_clock_peris * const peris =
+ (struct exynos7_clock_peris *)EXYNOS7_CMU_PERIS_BASE;
+
+struct exynos7_clock_topc {
+ uint32_t cci_pll_lock;
+ uint32_t bus0_pll_lock;
+ uint32_t bus1_pll_lock;
+ uint32_t mfc_pll_lock;
+ uint32_t aud_pll_lock;
+ uint32_t mif_pll_lock;
+ uint8_t res1[0xe8];
+ uint32_t cci_pll_con0;
+ uint32_t cci_pll_con1;
+ uint8_t res2[0x8];
+ uint32_t bus0_pll_con0;
+ uint32_t bus0_pll_con1;
+ uint8_t res3[0x8];
+ uint32_t bus1_pll_con0;
+ uint32_t bus1_pll_con1;
+ uint8_t res4[0x8];
+ uint32_t mfc_pll_con0;
+ uint32_t mfc_pll_con1;
+ uint8_t res5[0x8];
+ uint32_t aud_pll_con0;
+ uint32_t aud_pll_con1;
+ uint32_t aud_pll_con2;
+ uint8_t res6[0x4];
+ uint32_t mif_pll_con0;
+ uint32_t mif_pll_con1;
+ uint32_t mif_pll_con2;
+ uint8_t res7[0xa4];
+ uint32_t clk_mux_sel_topc0;
+ uint32_t clk_mux_sel_topc1;
+ uint32_t clk_mux_sel_topc2;
+ uint32_t clk_mux_sel_topc3;
+ uint32_t clk_mux_sel_topc4;
+ uint32_t clk_mux_sel_topc5;
+ uint8_t res8[0xe8];
+ uint32_t clk_mux_en_top_topc0;
+ uint32_t clk_mux_en_top_topc1;
+ uint32_t clk_mux_en_top_topc2;
+ uint32_t clk_mux_en_top_topc3;
+ uint32_t clk_mux_en_top_topc4;
+ uint32_t clk_mux_en_top_topc5;
+ uint8_t res9[0xe8];
+ uint32_t clk_mux_stat_top_topc0;
+ uint32_t clk_mux_stat_top_topc1;
+ uint32_t clk_mux_stat_top_topc2;
+ uint32_t clk_mux_stat_top_topc3;
+ uint32_t clk_mux_stat_top_topc4;
+ uint32_t clk_mux_stat_top_topc5;
+ uint8_t res10[0x1e8];
+ uint32_t clk_div_topc0;
+ uint32_t clk_div_topc1;
+ uint32_t clk_div_topc2;
+ uint32_t clk_div_topc3;
+ uint8_t res11[0xf0];
+ uint32_t clk_div_stat_topc0;
+ uint32_t clk_div_stat_topc1;
+ uint32_t clk_div_stat_topc2;
+ uint32_t clk_div_stat_topc3;
+ uint8_t res12[0xf0];
+ uint32_t clk_en_aclk_topc0;
+ uint32_t clk_en_aclk_topc1;
+ uint32_t clk_en_aclk_topc2;
+ uint8_t res13[0x1f4];
+ uint32_t clk_en_sclk_topc0;
+ uint32_t clk_en_sclk_topc1;
+ uint8_t res14[0xf8];
+ uint32_t clk_en_ip_topc;
+ uint8_t res15[0xfc];
+ uint32_t clkout_cmu_topc;
+ uint32_t clkout_all_blk_cmu;
+ uint8_t res16[0x8];
+ uint32_t clkout_cmu_topc_div_stat;
+ uint32_t clkout_all_blk_cmu_div_stat;
+ uint8_t res17[0xe8];
+ uint32_t cmu_topc_low_power_mode;
+ uint32_t cmu_topc_lp4_phy_div_sel;
+ uint32_t cmu_topc_rootclken_on;
+ uint8_t res18[0x2f8];
+ uint32_t drex_freq_ctrl1;
+ uint32_t pause;
+ uint8_t res19[0xf4];
+ uint32_t dvfs_ctrl_vdd_int;
+ uint8_t res20[0xc];
+ uint32_t dvfs_ctrl_vdd_disp_cam0;
+};
+
+static struct exynos7_clock_topc * const topc =
+ (struct exynos7_clock_topc *)EXYNOS7_CMU_TOPC_BASE;
+
+struct exynos7_clock_top0 {
+ uint8_t res1[0x4];
+ uint32_t isp_pll_lock;
+ uint32_t cam_pll_lock;
+ uint8_t res2[0x104];
+ uint32_t isp_pll_con0;
+ uint32_t isp_pll_con1;
+ uint8_t res3[0x8];
+ uint32_t cam_pll_con0;
+ uint32_t cam_pll_con1;
+ uint8_t res4[0xd8];
+ uint32_t clk_mux_sel_top00;
+ uint32_t clk_mux_sel_top01;
+ uint32_t clk_mux_sel_top02;
+ uint32_t clk_mux_sel_top03;
+ uint32_t clk_mux_sel_top04;
+ uint32_t clk_mux_sel_top05;
+ uint32_t clk_mux_sel_top06;
+ uint32_t clk_mux_sel_top07;
+ uint32_t clk_mux_sel_top0_disp;
+ uint32_t clk_mux_sel_top0_cam10;
+ uint32_t clk_mux_sel_top0_cam11;
+ uint8_t res5[0x4];
+ uint32_t clk_mux_sel_top0_peric0;
+ uint32_t clk_mux_sel_top0_peric1;
+ uint32_t clk_mux_sel_top0_peric2;
+ uint32_t clk_mux_sel_top0_peric3;
+ uint8_t res6[0xc0];
+ uint32_t clk_mux_en_top_top00;
+ uint32_t clk_mux_en_top_top01;
+ uint32_t clk_mux_en_top_top02;
+ uint32_t clk_mux_en_top_top03;
+ uint32_t clk_mux_en_top_top04;
+ uint32_t clk_mux_en_top_top05;
+ uint32_t clk_mux_en_top_top06;
+ uint32_t clk_mux_en_top_top07;
+ uint32_t clk_mux_en_top0_disp;
+ uint32_t clk_mux_en_top0_cam10;
+ uint32_t clk_mux_en_top0_cam11;
+ uint8_t res7[0x4];
+ uint32_t clk_mux_en_top0_peric0;
+ uint32_t clk_mux_en_top0_peric1;
+ uint32_t clk_mux_en_top0_peric2;
+ uint32_t clk_mux_en_top0_peric3;
+ uint8_t res8[0xc0];
+ uint32_t clk_mux_stat_top_top00;
+ uint32_t clk_mux_stat_top_top01;
+ uint32_t clk_mux_stat_top_top02;
+ uint32_t clk_mux_stat_top_top03;
+ uint32_t clk_mux_stat_top_top04;
+ uint32_t clk_mux_stat_top_top05;
+ uint32_t clk_mux_stat_top_top06;
+ uint32_t clk_mux_stat_top_top07;
+ uint32_t clk_mux_stat_top0_disp;
+ uint32_t clk_mux_stat_top0_cam10;
+ uint32_t clk_mux_stat_top0_cam11;
+ uint8_t res9[0x4];
+ uint32_t clk_mux_stat_top0_peric0;
+ uint32_t clk_mux_stat_top0_peric1;
+ uint32_t clk_mux_stat_top0_peric2;
+ uint32_t clk_mux_stat_top0_peric3;
+ uint8_t res10[0x1c0];
+ uint32_t clk_div_top00;
+ uint32_t clk_div_top01;
+ uint32_t clk_div_top02;
+ uint32_t clk_div_top03;
+ uint32_t clk_div_top04;
+ uint32_t clk_div_top05;
+ uint32_t clk_div_top06;
+ uint32_t clk_div_top07;
+ uint32_t clk_div_top0_disp;
+ uint32_t clk_div_top0_cam10;
+ uint32_t clk_div_top0_cam11;
+ uint8_t res11[0x4];
+ uint32_t clk_div_top0_peric0;
+ uint32_t clk_div_top0_peric1;
+ uint32_t clk_div_top0_peric2;
+ uint32_t clk_div_top0_peric3;
+ uint8_t re12[0xc0];
+ uint32_t clk_div_stat_top00;
+ uint32_t clk_div_stat_top01;
+ uint32_t clk_div_stat_top02;
+ uint32_t clk_div_stat_top03;
+ uint32_t clk_div_stat_top04;
+ uint32_t clk_div_stat_top05;
+ uint32_t clk_div_stat_top06;
+ uint32_t clk_div_stat_top07;
+ uint32_t clk_div_stat_top0_disp;
+ uint32_t clk_div_stat_top0_cam10;
+ uint32_t clk_div_stat_top0_cam11;
+ uint8_t res13[0x4];
+ uint32_t clk_div_stat_top0_peric0;
+ uint32_t clk_div_stat_top0_peric1;
+ uint32_t clk_div_stat_top0_peric2;
+ uint32_t clk_div_stat_top0_peric3;
+ uint8_t res14[0xc0];
+ uint32_t clk_en_aclk_top00;
+ uint32_t clk_en_aclk_top01;
+ uint32_t clk_en_aclk_top02;
+ uint32_t clk_en_aclk_top03;
+ uint32_t clk_en_aclk_top04;
+ uint32_t clk_en_aclk_top05;
+ uint32_t clk_en_aclk_top06;
+ uint32_t clk_en_aclk_top07;
+ uint8_t res15[0x200];
+ uint32_t clk_en_sclk_top0_disp;
+ uint32_t clk_en_sclk_top0_cam10;
+ uint32_t clk_en_sclk_top0_cam11;
+ uint8_t res16[0x4];
+ uint32_t clk_en_sclk_top0_peric0;
+ uint32_t clk_en_sclk_top0_peric1;
+ uint32_t clk_en_sclk_top0_peric2;
+ uint32_t clk_en_sclk_top0_peric3;
+ uint8_t res17[0xc0];
+ uint32_t clk_en_ip_top0;
+ uint8_t res18[0xfc];
+ uint32_t clkout_cmu_top0;
+ uint32_t clkout_cmu_top0_div_stat;
+ uint8_t res19[0xf8];
+ uint32_t mode_clock_en;
+ uint32_t cmu_top0_rootclken_on0;
+ uint32_t cmu_top0_rootclken_on1;
+ uint8_t res20[0xf4];
+ uint32_t cmu_top0_dvfs_ctrl_stat;
+};
+
+static struct exynos7_clock_top0 * const top0 =
+ (struct exynos7_clock_top0 *)EXYNOS7_CMU_TOP0_BASE;
+
+struct exynos7_clock_top1 {
+ uint8_t res1[0x200];
+ uint32_t clk_mux_sel_top10;
+ uint32_t clk_mux_sel_top11;
+ uint32_t clk_mux_sel_top12;
+ uint32_t clk_mux_sel_top13;
+ uint8_t res2[0x14];
+ uint32_t clk_mux_sel_top1_fsys0;
+ uint32_t clk_mux_sel_top1_fsys1;
+ uint32_t clk_mux_sel_top1_fsys11;
+ uint8_t res3[0xd0];
+ uint32_t clk_mux_en_top10;
+ uint32_t clk_mux_en_top11;
+ uint32_t clk_mux_en_top12;
+ uint32_t clk_mux_en_top13;
+ uint8_t res4[0x14];
+ uint32_t clk_mux_en_top1_fsys0;
+ uint32_t clk_mux_en_top1_fsys1;
+ uint32_t clk_mux_en_top1_fsys11;
+ uint8_t res5[0xd0];
+ uint32_t clk_mux_stat_top10;
+ uint32_t clk_mux_stat_top11;
+ uint32_t clk_mux_stat_top12;
+ uint32_t clk_mux_stat_top13;
+ uint8_t res6[0x14];
+ uint32_t clk_mux_stat_top1_fsys0;
+ uint32_t clk_mux_stat_top1_fsys1;
+ uint32_t clk_mux_stat_top1_fsys11;
+ uint8_t res7[0x1d0];
+ uint32_t clk_div_top10;
+ uint32_t clk_div_top11;
+ uint32_t clk_div_top12;
+ uint32_t clk_div_top13;
+ uint8_t res8[0x14];
+ uint32_t clk_div_top1_fsys0;
+ uint32_t clk_div_top1_fsys1;
+ uint32_t clk_div_top1_fsys11;
+ uint8_t res9[0xd0];
+ uint32_t clk_div_stat_top10;
+ uint32_t clk_div_stat_top11;
+ uint32_t clk_div_stat_top12;
+ uint32_t clk_div_stat_top13;
+ uint8_t res10[0x14];
+ uint32_t clk_div_stat_top1_fsys0;
+ uint32_t clk_div_stat_top1_fsys1;
+ uint32_t clk_div_stat_top1_fsys11;
+ uint8_t res11[0xd0];
+ uint32_t clk_en_aclk_top10;
+ uint32_t clk_en_aclk_top11;
+ uint32_t clk_en_aclk_top12;
+ uint32_t clk_en_aclk_top13;
+ uint8_t res12[0x214];
+ uint32_t clk_en_sclk_top1_fsys0;
+ uint32_t clk_en_sclk_top1_fsys1;
+ uint32_t clk_en_sclk_top1_fsys11;
+ uint8_t res13[0xd0];
+ uint32_t clk_en_ip_top1;
+ uint8_t res14[0xfc];
+ uint32_t clkout_cmu_top1;
+ uint32_t clkout_cmu_top1_div_stat;
+ uint8_t res15[0xfc];
+ uint32_t cmu_top1_rootclken_on;
+ uint8_t res16[0xf8];
+ uint32_t cmu_top1_dvfs_ctrl_stat;
+};
+
+static struct exynos7_clock_top1 * const top1 =
+ (struct exynos7_clock_top1 *)EXYNOS7_CMU_TOP1_BASE;
+
+unsigned long get_arm_clk(void);
+unsigned long get_i2c_clk(void);
+unsigned long get_mmc_clk(int dev_index);
+unsigned long get_pll_clk(int pllreg);
+unsigned long get_pwm_clk(void);
+unsigned long get_uart_clk(int dev_index);
+unsigned long get_usbdrd_clk(void);
+
+void set_mmc_clk(int dev_index, uint64_t div);
+void dmc_driver_freq(void);
+int system_clock_init(int is_resume);
+
+#endif /* _CPU_SAMSUNG_EXYNOS7_CLOCK_H_ */
diff --git a/src/soc/samsung/exynos7/include/soc/clock_init.h b/src/soc/samsung/exynos7/include/soc/clock_init.h
new file mode 100644
index 0000000..084fa2b
--- /dev/null
+++ b/src/soc/samsung/exynos7/include/soc/clock_init.h
@@ -0,0 +1,438 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _CPU_SAMSUNG_EXYNOS7_CLOCK_INIT_H_
+#define _CPU_SAMSUNG_EXYNOS7_CLOCK_INIT_H_
+
+/* Position and set M, P & S divider values */
+#define set_pll(mdiv, pdiv, sdiv) (mdiv << 16 | pdiv << 8 | sdiv << 0)
+
+/* Define PLLs */
+#define EXYNOS7_CCI_PLL 532
+#define EXYNOS7_BUS0_PLL 1600
+#define EXYNOS7_ISP_PLL 0
+#define EXYNOS7_CAM_PLL 0
+#define EXYNOS7_G3D_PLL 532
+#define EXYNOS7_AP_PLL 900
+#define EXYNOS7_MIF_PLL 1264
+
+/* Set clock enable */
+#define ENABLE(x) (x << 31)
+#define ENABLE_SDIV_CLKSTOP(x) (x << 16)
+#define ENABLE_MDIV_CLKSTOP(x) (x << 5)
+
+/* MIF Pause */
+#define PAUSE_MIF(x) (x << 20)
+
+/* AP0 clock divider */
+#define AP_PCLK_DBG_RATIO(x) (x << 26)
+#define AP_ATCLK_RATIO(x) (x << 20)
+#define AP_PCLK_AP_RATIO(x) (x << 12)
+#define AP_ACLK_AP_RATIO(x) (x << 8)
+#define AP_AP2_RATIO(x) (x << 4)
+#define AP_AP1_RATIO(x) (x << 0)
+
+/* AP1 clock divider */
+#define AP_CNTCLK_RATIO(x) (x << 8)
+#define AP_SCLK_HPM_AP_RATIO(x) (x << 4)
+#define AP_AP_PLL_RATIO(x) (x << 0)
+
+/* AUD0 clock divider */
+#define AUD_PCLK_DBG_AUD_RATIO(x) (x << 8)
+#define AUD_ACLK_AUD_RATIO(x) (x << 4)
+#define AUD_CA5_RATIO(x) (x << 0)
+
+/* AUD1 clock divider */
+#define AUD_CDCLK_RATIO(x) (x << 24)
+#define AUD_SCLK_SLIMBUS_RATIO(x) (x << 16)
+#define AUD_SCLK_UART_RATIO(x) (x << 12)
+#define AUD_SCLK_PCM_RATIO(x) (x << 4)
+#define AUD_SCLK_I2S_RATIO(x) (x << 0)
+
+/* BUS0 clock divider */
+#define PCLK_BUS0_133_RATIO(x) (x << 0)
+
+/* BUS1 clock divider */
+#define PCLK_BUS1_133_RATIO(x) (x << 0)
+
+/* CCORE clock divider */
+#define ACLK_CCORE_266_RATIO(x) (x << 0)
+
+/* DISP clock divider */
+#define DISP_SCLK_DECON_INT_ECLK_RATIO(x) (x << 20)
+#define DISP_SCLK_DECON_EXT_ECLK_RATIO(x) (x << 16)
+#define DISP_SCLK_DECON_INT_EXTCLKPLL_RATIO(x) (x << 12)
+#define DISP_SCLK_DECON_EXT_EXTCLKPLL_RATIO(x) (x << 8)
+#define DISP_PCLK_DISP_RATIO(x) (x << 0)
+
+/* FSYS0 clock divider */
+#define FSYS0_USB20_RATIO(x) (x << 4)
+#define FSYS0_PCLK_FSYS0_RATIO(x) (x << 0)
+
+/* FSYS1 clock divider */
+#define FSYS1_PCLK_FSYS1_RATIO(x) (x << 0)
+
+/* G2D clock divider */
+#define G2D_PCLK_G2D_RATIO(x) (x << 0)
+
+/* G3D clock divider */
+#define G3D_SCLK_HPM_G3D_RATIO(x) (x << 8)
+#define G3D_PCLK_G3D_RATIO(x) (x << 4)
+#define G3D_ACLK_G3D_RATIO(x) (x << 0)
+
+/* HEVC clock divider */
+#define HEVC_PCLK_HEVC_RATIO(x) (x << 0)
+
+/* MFC clock divider */
+#define MFC_PCLK_MFC_PROMISE_RATIO(x) (x << 4)
+#define MFC_PCLK_MFC_RATIO(x) (x << 0)
+
+/* MIF clock divider */
+#define MIF_SCLK_HPM_MIF_RATIO(x) (x << 4)
+#define MIF_PCLK_MIF_RATIO(x) (x << 0)
+
+/* MSCL clock divider */
+#define MSCL_PCLK_MSCL_RATIO(x) (x << 0)
+
+/* TOPC3 clock divider */
+#define SCLK_AUD_PLL_RATIO(x) (x << 24)
+#define SCLK_BUS_PLL_G3D_RATIO(x) (x << 20)
+#define SCLK_MFC_PLL_RATIO(x) (x << 16)
+#define SCLK_CCI_PLL_RATIO(x) (x << 12)
+#define SCLK_BUS1_PLL_RATIO(x) (x << 8)
+#define SCLK_BUS0_PLL_MIF_RATIO(x) (x << 4)
+#define SCLK_BUS0_PLL_RATIO(x) (x << 0)
+
+/* AP Mux Select */
+#define AP_BUS_PLL_USER_SEL(x) (x << 0)
+#define AP_SEL(x) (x << 0)
+#define AP_PLL_SEL(x) (x << 0)
+
+/* AUD Mux select */
+#define AUD_PLL_USER_SEL(x) (x << 20)
+#define AUD_SCLK_PCM_SEL(x) (x << 16)
+#define AUD_SCLK_I2S_SEL(x) (x << 12)
+
+/* BUS0 Mux select */
+#define ACLK_BUS0_532_USER_SEL(x) (x << 0)
+
+/* BUS1 Mux select */
+#define ACLK_BUS1_200_USER_SEL(x) (x << 4)
+#define ACLK_BUS1_532_USER_SEL(x) (x << 0)
+
+/* CCORE Mux select */
+#define ACLK_CCORE_133_USER_SEL(x) (x << 1)
+#define ACLK_CCORE_532_USER_SEL(x) (x << 0)
+
+/* DISP0 Mux select */
+#define DISP0_PLL_SEL(x) (x << 28)
+#define DISP0_ACLK_DISP_400_USER_SEL(x) (x << 24)
+
+/* DISP1 Mux select */
+#define DISP1_SCLK_DECON_INT_ECLK(x) (x << 28)
+#define DISP1_SCLK_DECON_EXT_ECLK(x) (x << 24)
+#define DISP1_SCLK_DECON_VCLK(x) (x << 20)
+#define DISP1_SCLK_DSD(x) (x << 16)
+
+/* DISP2 Mux select */
+#define DISP2_PHYCLK_HDMIPHY_PIXEL_CLKO(x) (x << 20)
+#define DISP2_PHYCLK_HDMIPHY_TMDS_CLKO(x) (x << 16)
+#define DISP2_PHYCLK_MIPIDPHY0_RXCLKESC0(x) (x << 12)
+#define DISP2_PHYCLK_MIPIDPHY0_BITCLKDIV8(x) (x << 8)
+#define DISP2_PHYCLK_MIPIDPHY1_RXCLKESC0(x) (x << 4)
+#define DISP2_PHYCLK_MIPIDPHY1_BITCLKDIV8(x) (x << 0)
+
+/* DISP3 Mux select */
+#define DISP3_SCLK_DECON_INT_ECLK(x) (x << 20)
+#define DISP3_SCLK_DECON_EXT_ECLK(x) (x << 16)
+#define DISP3_SCLK_DECON_INT_EXTCLKPLL(x) (x << 12)
+#define DISP3_SCLK_DECON_EXT_EXTCLKPLL(x) (x << 8)
+
+/* FSYS00 Mux select */
+#define FSYS0_HSIC_PLL_SEL(x) (x << 28)
+#define FSYS0_ACLK_FSYS0_200(x) (x << 24)
+#define FSYS0_PHYCLK_SEL0(x) (x << 20)
+#define FSYS0_PHYCLK_SEL1(x) (x << 16)
+
+/* FSYS01 Mux select */
+#define FSYS0_SCLK_USBDRD300(x) (x << 28)
+#define FSYS0_SCLK_MMC2(x) (x << 24)
+#define FSYS0_SCLK_UFSUNIPRO11(x) (x << 20)
+#define FSYS0_SCLK_PHY_FSYS0(x) (x << 16)
+
+/* FSYS02 Mux select */
+#define FSYS0_PHYCLK_USBDRD300_UDRD30_PHYCLOCK(x) (x << 28)
+#define FSYS0_PHYCLK_USBDRD300_UDRD30_PIPE_PCLK(x) (x << 24)
+#define FSYS0_PHYCLK_USBHOST20_PHY_FREECLK__HSIC1(x) (x << 20)
+#define FSYS0_PHYCLK_USBHOST20_PHY_PHYCLK__HSIC1(x) (x << 16)
+
+/* FSYS03 Mux select */
+#define FSYS0_PHYCLK_UFS_TX0_SYMBOL(x) (x << 28)
+#define FSYS0_PHYCLK_UFS_RX0_SYMBOL(x) (x << 24)
+#define FSYS0_PHYCLK_LLI_TX0_SYMBOL(x) (x << 20)
+#define FSYS0_PHYCLK_LLI_RX0_SYMBOL(x) (x << 16)
+#define FSYS0_PHYCLK_PCIE_TX0(x) (x << 12)
+#define FSYS0_PHYCLK_PCIE_RX0(x) (x << 8)
+
+/* FSYS10 Mux select */
+#define FSYS1_ACLK_FSYS1_200(x) (x << 28)
+#define FSYS1_PHYCLK_SEL0(x) (x << 20)
+#define FSYS1_PHYCLK_SEL1(x) (x << 16)
+
+/* FSYS11 Mux select */
+#define FSYS1_SCLK_MMC0(x) (x << 28)
+#define FSYS1_SCLK_MMC1(x) (x << 24)
+#define FSYS1_SCLK_UFSUNIPRO20(x) (x << 20)
+#define FSYS1_SCLK_PHY_FSYS1(x) (x << 16)
+#define FSYS1_SCLK_TLX400_WIFI1(x) (x << 12)
+
+/* FSYS12 Mux select */
+#define FSYS1_PHYCLK_UFS20_TX0_SYMBOL(x) (x << 28)
+#define FSYS1_PHYCLK_UFS20_RX0_SYMBOL(x) (x << 24)
+#define FSYS1_PHYCLK_UFS20_RX1_SYMBOL(x) (x << 16)
+#define FSYS1_PHYCLK_PCIE_WIFI1_TX0(x) (x << 12)
+#define FSYS1_PHYCLK_PCIE_WIFI1_RX0(x) (x << 8)
+
+/* G2D Mux select */
+#define G2D_ACLK_G2D_266_USER_SEL(x) (x << 4)
+#define G2D_ACLK_G2D_400_USER_SEL(x) (x << 0)
+
+/* G3D Mux select */
+#define G3D_SEL(x) (x << 8)
+#define G3D_SCLK_BUS_PLL_G3D_USER_SEL(x) (x << 4)
+#define G3D_PLL_SEL(x) (x << 0)
+
+/* HEVC Mux select */
+#define HEVC_ACLK_HEVC_532_USER_SEL(x) (x << 0)
+
+/* IMEM Mux select */
+#define ACLK_IMEM_100_USER_SEL(x) (x << 8)
+#define ACLK_IMEM_200_USER_SEL(x) (x << 4)
+#define ACLK_IMEM_266_USER_SEL(x) (x << 0)
+
+/* MFC Mux select */
+#define MFC_ACLK_MFC_BUS_532_USER_SEL(x) (x << 4)
+#define MFC_ACLK_MFC_532_USER_SEL(x) (x << 0)
+
+/* MIF Mux select */
+#define MIF_ACLK_MIF_PLL_CLK_MUX_SEL(x) (x << 16)
+#define MIF_MIF_PLL_USER_SEL(x) (x << 12)
+#define MIF_SCLK_HPM_MIF_SEL(x) (x << 8)
+#define MIF_PCLK_MIF_SEL(x) (x << 4)
+#define MIF_ACLK_MIF_USER_SEL(x) (x << 0)
+
+/* MSCL Mux select */
+#define MSCL_ACLK_MSCL_532_USER_SEL(x) (x << 0)
+
+/* PERIC0 Mux select */
+#define PERIC0_SCLK_UART0_USER_SEL(x) (x << 16)
+#define PERIC0_ACLK_PERIC0_66_USER_SEL(x) (x << 0)
+
+/* PERIC10 Mux select */
+#define PERIC10_ACLK_PERIC1_66_USER_SEL(x) (x << 0)
+
+/* PERIC11 Mux select */
+#define PERIC11_SCLK_UART3_USER_SEL(x) (x << 28)
+#define PERIC11_SCLK_UART2_USER_SEL(x) (x << 24)
+#define PERIC11_SCLK_UART1_USER_SEL(x) (x << 20)
+#define PERIC11_SCLK_SPI4_USER_SEL(x) (x << 16)
+#define PERIC11_SCLK_SPI3_USER_SEL(x) (x << 12)
+#define PERIC11_SCLK_SPI2_USER_SEL(x) (x << 8)
+#define PERIC11_SCLK_SPI1_USER_SEL(x) (x << 4)
+#define PERIC11_SCLK_SPI0_USER_SEL(x) (x << 0)
+
+/* PERIS Mux select */
+#define ACLK_PERIS_66_USER_SEL(x) (x << 0)
+
+/* TOP00 Mux select */
+#define TOP00_ISP_PLL_SEL(x) (x << 24)
+#define TOP00_CAM_PLL_SEL(x) (x << 20)
+#define TOP00_BUS0_PLL_USER_SEL(x) (x << 16)
+#define TOP00_BUS1_PLL_USER_SEL(x) (x << 12)
+#define TOP00_CCI_PLL_USER_SEL(x) (x << 8)
+#define TOP00_MFC_PLL_USER_SEL(x) (x << 4)
+#define TOP00_AUD_PLL_USER_SEL(x) (x << 0)
+
+/* TOP01 Mux select */
+#define TOP01_SCLK_CMU0_APBIF_SEL(x) (x << 28)
+#define TOP01_HALF_BUS0_PLL_USER(x) (x << 16)
+#define TOP01_HALF_BUS1_PLL_USER(x) (x << 12)
+#define TOP01_HALF_CCI_PLL_USER(x) (x << 8)
+#define TOP01_HALF_MFC_PLL_USER(x) (x << 4)
+
+/* TOP10 Mux select */
+#define TOP10_BUS0_PLL_USER_SEL(x) (x << 16)
+#define TOP10_BUS1_PLL_USER_SEL(x) (x << 12)
+#define TOP10_CCI_PLL_USER_SEL(x) (x << 8)
+#define TOP10_MFC_PLL_USER_SEL(x) (x << 4)
+
+/* TOP11 Mux select */
+#define TOP11_SCLK_CMU1_APBIF_SEL(x) (x << 28)
+#define TOP11_HALF_BUS0_PLL_USER(x) (x << 16)
+#define TOP11_HALF_BUS1_PLL_USER(x) (x << 12)
+#define TOP11_HALF_CCI_PLL_USER(x) (x << 8)
+#define TOP11_HALF_MFC_PLL_USER(x) (x << 4)
+
+/* TOPC0 Mux select */
+#define TOPC0_SCLK_MFC_PLL_CMUC_SEL(x) (x << 28)
+#define TOPC0_SCLK_CCI_PLL_CMUC_SEL(x) (x << 24)
+#define TOPC0_SCLK_BUS1_PLL_CMUC_SEL(x) (x << 20)
+#define TOPC0_SCLK_BUS0_PLL_CMUC_SEL(x) (x << 16)
+#define TOPC0_MFC_PLL_SEL(x) (x << 12)
+#define TOPC0_CCI_PLL_SEL(x) (x << 8)
+#define TOPC0_BUS1_PLL_SEL(x) (x << 4)
+#define TOPC0_BUS0_PLL_SEL(x) (x << 0)
+
+/* TOPC1 Mux select */
+#define TOPC1_SCLK_BUS_PLL_G3D_SEL(x) (x << 20)
+#define TOPC1_SCLK_BUS0_PLL_OUT_SEL(x) (x << 16)
+#define TOPC1_SCLK_BUS0_PLL_MIF_SEL(x) (x << 12)
+#define TOPC1_SCLK_BUS0_PLL_AP_SEL(x) (x << 4)
+#define TOPC1_AUD_PLL_SEL(x) (x << 0)
+
+/* TOPC5 Mux select */
+#define TOPC5_MIF_ACLK_MIF_PLL_SEL(x) (x << 20)
+#define TOPC5_MIF_PLL_USER_SEL(x) (x << 16)
+#define TOPC5_MIF_ACLK_MIF_USER_SEL(x) (x << 12)
+#define TOPC5_MIF_ACLK_MIF_SEL(x) (x << 8)
+#define TOPC5_MIF_PLL_SEL(x) (x << 0)
+
+/* TOPC0 clock divider & TOPC2 Mux select */
+#define ACLK_IMEM_100(x) (x << 28)
+#define ACLK_IMEM_200(x) (x << 24)
+#define ACLK_IMEM_266(x) (x << 20)
+#define ACLK_BUS1_200(x) (x << 16)
+#define ACLK_BUS1_532(x) (x << 12)
+#define ACLK_BUS0_532(x) (x << 8)
+#define ACLK_CCORE_133(x) (x << 4)
+#define ACLK_CCORE_532(x) (x << 0)
+
+/* TOPC1 clock divider & TOPC3 Mux select */
+#define ACLK_PERIS_66(x) (x << 24)
+#define ACLK_MSCL_532(x) (x << 20)
+#define ACLK_MFC_BUS_532(x) (x << 16)
+#define ACLK_HEVC_532(x) (x << 12)
+#define ACLK_MFC_532(x) (x << 8)
+#define ACLK_G2D_266(x) (x << 4)
+#define ACLK_G2D_400(x) (x << 0)
+
+/* TOPC2 clock divider & TOPC4 Mux select */
+#define SCLK_CMU_APBIF(x) (x << 0)
+
+/* TOP03 clock divider & TOP03 Mux select */
+#define ACLK_DISP_400(x) (x << 28)
+#define ACLK_PERIC0_66(x) (x << 20)
+#define ACLK_PERIC1_66(x) (x << 12)
+#define ACLK_VPP0_400(x) (x << 8)
+#define ACLK_VPP1_400(x) (x << 4)
+
+/* TOP04 clock divider & TOP04 Mux select */
+#define ACLK_ISP0_ISP0_590(x) (x << 28)
+#define ACLK_ISP0_TPU_590(x) (x << 24)
+#define ACLK_ISP0_TREX_532(x) (x << 20)
+#define ACLK_ISP1_ISP1_468(x) (x << 16)
+#define ACLK_ISP1_AHB_117(x) (x << 12)
+
+/* TOP05 clock divider & TOP05 Mux select */
+#define ACLK_CAM0_CSIS0_690(x) (x << 28)
+#define ACLK_CAM0_BNSA_690(x) (x << 24)
+#define ACLK_CAM0_BNSB_690(x) (x << 20)
+#define ACLK_CAM0_BNSD_690(x) (x << 16)
+#define ACLK_CAM0_CSIS1_174(x) (x << 12)
+
+/* TOP06 clock divider & TOP06 Mux select */
+#define ACLK_CAM0_3AA0_690(x) (x << 28)
+#define ACLK_CAM0_3AA1_468(x) (x << 24)
+#define ACLK_CAM0_TREX_532(x) (x << 20)
+#define ACLK_CAM0_NOCP_133(x) (x << 16)
+
+/* TOP07 clock divider & TOP07 Mux select */
+#define ACLK_CAM1_SCLVRA_491(x) (x << 28)
+#define ACLK_CAM1_ARM_668(x) (x << 24)
+#define ACLK_CAM1_BUSPERI_334(x) (x << 20)
+#define ACLK_CAM1_BNSCSIS_133(x) (x << 16)
+#define ACLK_CAM1_NOCP_133(x) (x << 12)
+#define ACLK_CAM1_TREX_532(x) (x << 8)
+
+/* TOP0-DISP clock divider & TOP0-DISP Mux select */
+#define SCLK_DECON_INT_ECLK(x) (x << 28)
+#define SCLK_DECON_EXT_ECLK(x) (x << 24)
+#define SCLK_DECON_VCLK(x) (x << 20)
+#define SCLK_DSD(x) (x << 16)
+#define SCLK_HDMI_SPDIF(x) (x << 12)
+
+/* TOP0-CAM10 clock divider & TOP0-CAM10 Mux select */
+#define SCLK_ISP_SPI0(x) (x << 20)
+#define SCLK_ISP_SPI1(x) (x << 8)
+#define SCLK_ISP_UART(x) (x << 4)
+
+/* TOP0-CAM11 clock divider & TOP0-CAM11 Mux select */
+#define SCLK_ISP_PWM(x) (x << 28)
+#define SCLK_ISP_MPWM(x) (x << 24)
+#define SCLK_ISP_SENSOR0(x) (x << 16)
+#define SCLK_ISP_SENSOR1(x) (x << 8)
+#define SCLK_ISP_SENSOR2(x) (x << 0)
+
+/* TOP0-PERIC0 clock divider & TOP0-PERIC0 Mux select */
+#define SCLK_I2S1(x) (x << 20)
+#define SCLK_PCM1(x) (x << 8)
+#define SCLK_SPDIF(x) (x << 4)
+
+/* TOP0-PERIC1 clock divider & TOP0-PERIC1 Mux select */
+#define SCLK_I2S1(x) (x << 20)
+#define SCLK_SPI0(x) (x << 20)
+#define SCLK_SPI1(x) (x << 8)
+
+/* TOP0-PERIC2 clock divider & TOP0-PERIC2 Mux select */
+#define SCLK_I2S1(x) (x << 20)
+#define SCLK_SPI2(x) (x << 20)
+#define SCLK_SPI3(x) (x << 8)
+
+/* TOP0-PERIC3 clock divider & TOP0-PERIC3 Mux select */
+#define SCLK_I2S1(x) (x << 20)
+#define SCLK_SPI4(x) (x << 20)
+#define SCLK_UART0(x) (x << 16)
+#define SCLK_UART1(x) (x << 12)
+#define SCLK_UART2(x) (x << 8)
+#define SCLK_UART3(x) (x << 4)
+
+/* TOP13 clock divider & TOP13 Mux select */
+#define ACLK_FSYS0_200(x) (x << 28)
+#define ACLK_FSYS1_200(x) (x << 24)
+
+/* TOP1-FSYS0 clock divider & TOP1-FSYS0 Mux select */
+#define SCLK_USBDRD300(x) (x << 28)
+#define SCLK_MMC2(x) (x << 24)
+#define SCLK_UFSUNIPRO11(x) (x << 16)
+#define SCLK_PHY_FSYS0(x) (x << 8)
+#define SCLK_PHY_FSYS0_26M(x) (x << 0)
+
+/* TOP1-FSYS1 clock divider & TOP1-FSYS1 Mux select */
+#define SCLK_MMC0(x) (x << 28)
+#define SCLK_MMC1(x) (x << 24)
+#define SCLK_UFSUNIPRO20(x) (x << 16)
+#define SCLK_TLX400_WIFI1(x) (x << 8)
+#define SCLK_PHY_FSYS1(x) (x << 0)
+
+/* TOP1-FSYS11 clock divider & TOP1-FSYS11 Mux select */
+#define SCLK_PHY_FSYS1_26M(x) (x << 24)
+
+#define FIN 24
+
+#endif /* _CPU_SAMSUNG_EXYNOS7_CLOCK_INIT_H_ */
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