[coreboot-gerrit] New patch to review for coreboot: soc/apollolake: Use simpler macros for the northbridge PCI device
Alexandru Gagniuc (alexandrux.gagniuc@intel.com)
gerrit at coreboot.org
Wed May 18 19:41:38 CEST 2016
Alexandru Gagniuc (alexandrux.gagniuc at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14890
-gerrit
commit f21d082b5c298cf0a16ca34d29a75cba612916ad
Author: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
Date: Wed May 18 10:26:53 2016 -0700
soc/apollolake: Use simpler macros for the northbridge PCI device
I found this when I was looking at the NB_DEV_ROOT macro, and trying
to understand the PCI address of the device it referenced. After ten
or so minutes of dead ends and decoding stringified macros, I found
the system to be quite ingenious in the way it encoded the PCI address
or called dev_find_slot() behind the curtains.
On the other hand, it's almost unreadable, so rewrite the macro in
terms of more basic and readable macros.
Change-Id: I9b7071d67c8d58926e9b01fadaa239db1120448c
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
---
src/soc/intel/apollolake/bootblock/bootblock.c | 2 +-
src/soc/intel/apollolake/chip.c | 2 +-
src/soc/intel/apollolake/include/soc/pci_devs.h | 12 +++---------
src/soc/intel/apollolake/memmap.c | 4 +++-
src/soc/intel/apollolake/romstage.c | 2 +-
5 files changed, 9 insertions(+), 13 deletions(-)
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index cd23f59..bafd6af 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -50,7 +50,7 @@ static void enable_pm_timer(void)
void asmlinkage bootblock_c_entry(void)
{
- device_t dev = NB_DEV_ROOT;
+ device_t dev = NORTHBRIDGE_DEV;
/* Set PCI Express BAR */
pci_io_write_config32(dev, PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | 1);
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index f56e1f2..23dc892 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -100,7 +100,7 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
/* Load VBT before devicetree-specific config. */
silconfig->GraphicsConfigPtr = (uintptr_t)vbt;
- struct device *dev = NB_DEV_ROOT;
+ struct device *dev = dev_find_slot(NB_BUS, NB_DEVFN);
if (!dev || !dev->chip_info) {
printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
return;
diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h
index ec550e8..5717aae 100644
--- a/src/soc/intel/apollolake/include/soc/pci_devs.h
+++ b/src/soc/intel/apollolake/include/soc/pci_devs.h
@@ -17,26 +17,17 @@
#include <rules.h>
-#define _NB_DEVFN(slot) PCI_DEVFN(NB_DEV_SLOT_ ## slot, 0)
#define _LPSS_PCI_DEVFN(slot, func) PCI_DEVFN(LPSS_DEV_SLOT_##slot, func)
-
#if !defined(__SIMPLE_DEVICE__)
#include <device/device.h>
#include <device/pci_def.h>
-#define _NB_DEV(slot) dev_find_slot(0, _NB_DEVFN(slot))
#define _LPSS_PCI_DEV(slot, func) dev_find_slot(0, _LPSS_PCI_DEVFN(slot, func))
#else
#include <arch/io.h>
-#define _NB_DEV(slot) PCI_DEV(0, NB_DEV_SLOT_ ## slot, 0)
#define _LPSS_PCI_DEV(slot, func) PCI_DEV(0, LPSS_DEV_SLOT_##slot, func)
#endif
-/* North bridge devices */
-#define NB_DEV_SLOT_ROOT 0x00
-#define NB_DEVFN_ROOT _NB_DEVFN(ROOT)
-#define NB_DEV_ROOT _NB_DEV(ROOT)
-
/* LPSS UART */
#define LPSS_DEV_SLOT_UART 0x18
#define LPSS_DEVFN_UART0 _LPSS_PCI_DEVFN(UART, 0)
@@ -48,6 +39,9 @@
#define LPSS_DEV_UART2 _LPSS_PCI_DEV(UART, 2)
#define LPSS_DEV_UART3 _LPSS_PCI_DEV(UART, 3)
+#define NB_BUS 0
+#define NB_DEVFN PCI_DEVFN(0, 0)
+#define NORTHBRIDGE_DEV PCI_DEV(0, 0x0, 0)
#define P2SB_DEV PCI_DEV(0, 0xd, 0)
#define PMC_DEV PCI_DEV(0, 0xd, 1)
#define SPI_DEV PCI_DEV(0, 0xd, 2)
diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c
index bf172cb..f182bc6 100644
--- a/src/soc/intel/apollolake/memmap.c
+++ b/src/soc/intel/apollolake/memmap.c
@@ -15,6 +15,8 @@
* GNU General Public License for more details.
*/
+#define __SIMPLE_DEVICE__
+
#include <arch/io.h>
#include <cbmem.h>
#include <device/pci.h>
@@ -23,7 +25,7 @@
static uintptr_t smm_region_start(void)
{
- return ALIGN_DOWN(pci_read_config32(NB_DEV_ROOT, TSEG), 1*MiB);
+ return ALIGN_DOWN(pci_read_config32(NORTHBRIDGE_DEV, TSEG), 1*MiB);
}
void *cbmem_top(void)
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index cfef483..864c990 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -72,7 +72,7 @@ static void soc_early_romstage_init(void)
device_t pmc = PMC_DEV;
/* Set MCH base address and enable bit */
- pci_write_config32(NB_DEV_ROOT, MCHBAR, MCH_BASE_ADDR | 1);
+ pci_write_config32(NORTHBRIDGE_DEV, MCHBAR, MCH_BASE_ADDR | 1);
/* Set PMC base addresses and enable decoding. */
pci_write_config32(pmc, PCI_BASE_ADDRESS_0, PMC_BAR0);
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