[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: clear up ACPI timer emulation magic constant

[Aaron Durbin (adurbin@chromium.org)]

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14889

-gerrit

commit 12f3881ff8eba53b1c977f80452b0ed1fd800330
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed May 18 11:08:39 2016 -0500

    soc/intel/apollolake: clear up ACPI timer emulation magic constant
    
    The timer emulation works by deriving a frequency based off the
    Common Timer Copy with a frequency of 19.2MHz.
    The desired frequency = (19.2MHz * multiplier) >> 32;
    With that knowledge update the code to let the compiler perform
    the necessary math based on target frequency.
    
    Change-Id: I716c7980f0456a7c6072bbaaddd6b7fcd8cd5b37
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/apollolake/bootblock/bootblock.c | 9 +++++++--
 src/soc/intel/apollolake/include/soc/cpu.h     | 3 +++
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index cd23f59..77d98d9 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -41,8 +41,13 @@ static void enable_pm_timer(void)
 {
 	/* ACPI PM timer emulation */
 	msr_t msr;
-	/* Multiplier value that somehow 3.579545MHz freq */
-	msr.hi = 0x2FBA2E25;
+	/*
+	 * The derived frequency is calculated as follows:
+	 *    (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
+	 * Back solve the multiplier so the 3.579545MHz ACPI timer
+	 * frequency is used.
+	 */
+	msr.hi = (3579545ULL << 32) / CTC_FREQ;
 	/* Set PM1 timer IO port and enable*/
 	msr.lo = EMULATE_PM_TMR_EN | (ACPI_PMIO_BASE + R_ACPI_PM1_TMR);
 	wrmsr(MSR_EMULATE_PM_TMR, msr);
diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h
index b731d4f..78fc0b0 100644
--- a/src/soc/intel/apollolake/include/soc/cpu.h
+++ b/src/soc/intel/apollolake/include/soc/cpu.h
@@ -37,4 +37,7 @@ void apollolake_init_cpus(struct device *dev);
 
 #define BASE_CLOCK_MHZ		100
 
+/* Common Timer Copy (CTC) frequency - 19.2MHz. */
+#define CTC_FREQ 19200000
+
 #endif /* _SOC_APOLLOLAKE_CPU_H_ */