[coreboot-gerrit] New patch to review for coreboot: DO NOT MERGE

[Leroy P Leahy (leroy.p.leahy@intel.com)]

Leroy P Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14873

-gerrit

commit 1409ce2244f0cc2be4016a07ab35250e9822affe
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date:   Wed Apr 6 09:19:32 2016 -0700

    DO NOT MERGE
    
    Change-Id: I9b8b54da29659c6be9107d7d4ab17e3f7cd55642
---
 src/drivers/intel/fsp1_1/stack.c        |  4 ++--
 src/soc/intel/quark/include/soc/iomap.h |  4 ++++
 src/soc/intel/quark/romstage/romstage.c | 13 +++++++++++++
 3 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/src/drivers/intel/fsp1_1/stack.c b/src/drivers/intel/fsp1_1/stack.c
index e048229..4cf0315 100644
--- a/src/drivers/intel/fsp1_1/stack.c
+++ b/src/drivers/intel/fsp1_1/stack.c
@@ -153,11 +153,11 @@ void *setup_stack_and_mtrrs(void)
 	num_mtrrs++;
 #endif
 
-	/* Cache the ROM as WP just below 4GiB. */
+	/* Cache the ROM as WB just below 4GiB. */
 	slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */
 	slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID);
 	slot = stack_push32(slot, 0); /* upper base */
-	slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
+	slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRBACK);
 	num_mtrrs++;
 
 	/* Validate the MTRR usage */
diff --git a/src/soc/intel/quark/include/soc/iomap.h b/src/soc/intel/quark/include/soc/iomap.h
index ce92676..fbe6a0f 100644
--- a/src/soc/intel/quark/include/soc/iomap.h
+++ b/src/soc/intel/quark/include/soc/iomap.h
@@ -27,6 +27,10 @@
 /* I2C/GPIO Controller */
 #define I2C_GPIO_BASE_ADDRESS		0xa0020000
 
+/* Legacy Bridge */
+#define LEGACY_BRIDGE_BASE_ADDRESS      0xfec00000
+#define LEGACY_BRIDGE_SIZE              0x00200000
+
 /*
  * I/O port address space
  */
diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c
index 2f16c5f..f876d3e 100644
--- a/src/soc/intel/quark/romstage/romstage.c
+++ b/src/soc/intel/quark/romstage/romstage.c
@@ -19,6 +19,7 @@
 #include <console/console.h>
 #include <cbfs.h>
 #include "../chip.h"
+#include <cpu/x86/mtrr.h>
 #include <device/pci_def.h>
 #include <fsp/car.h>
 #include <fsp/util.h>
@@ -54,6 +55,18 @@ void car_soc_pre_console_init(void)
 
 void car_soc_post_console_init(void)
 {
+	union {
+		uint32_t u32[2];
+		msr_t msr;
+	} value;
+
+	value.u32[0] = ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRBACK;
+	value.u32[1] = ~(CONFIG_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID;
+	soc_mtrr_write(MTRR_PHYS_BASE(0), value.msr);
+	value.msr = soc_mtrr_read(MTRR_PHYS_BASE(0));
+
+soc_display_mtrrs();
+
 	report_platform_info();
 
 	/* Initialize the controllers */