[coreboot-gerrit] New patch to review for coreboot: WIP: workaround some Apollolake FSP issues

[Bora Guvendik (bora.guvendik@intel.com)]

Bora Guvendik (bora.guvendik at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14804

-gerrit

commit 37274fb1f6f31122b867be3242f832800a2eeeef
Author: Andrey Petrov <andrey.petrov at intel.com>
Date:   Sat Apr 23 14:28:21 2016 -0700

    WIP: workaround some Apollolake FSP issues
    
    CAR needs to be set to 1MiB, and romstage linked at different address, since
    FSP blobs can't be relocated and does not accept StackBase parameter.
    
    BUG=chrome-os-partner:51844
    BRANCH=none
    TEST=boots to chrome OS
    
    Change-Id: I56f78f043099dc835e294dbc081d7506bfad280d
    Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
 src/soc/intel/apollolake/Kconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index ba95f15..97900f9 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -71,7 +71,7 @@ config DCACHE_RAM_BASE
 
 config DCACHE_RAM_SIZE
 	hex "Length in bytes of cache-as-RAM"
-	default 0x80000
+	default 0x100000
 	help
 	  The size of the cache-as-ram region required during bootblock
 	  and/or romstage.
@@ -114,7 +114,7 @@ config X86_TOP4G_BOOTMEDIA_MAP
 
 config ROMSTAGE_ADDR
 	hex
-	default 0xfef2e000
+	default 0xfef3e000
 	help
 	  The base address (in CAR) where romstage should be linked