[coreboot-gerrit] Patch merged into coreboot/master: drivers/uart: Enable override for input clock divider

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 148762110c8a00c88b8e0326ec69dc7392bf3739
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date:   Wed May 4 13:13:20 2016 -0700

    drivers/uart: Enable override for input clock divider
    
    Allow the platform to override the input clock divider by adding the
    uart_input_clock_divider routine.  This routine combines the baud-rate
    oversample divider with any other input clock divider.  The default
    routine returns 16 which is the standard baud-rate oversampling value.
    A platform may override this default "weak" routine by providing a new
    routine and selecting UART_OVERRIDE_INPUT_CLOCK_DIVIDER.  This works
    around ROMCC not supporting weak routines.
    
    Testing on Galileo:
    *  Edit the src/mainboard/intel/galileo/Makefile.inc file:
       *  Add "select ADD_FSP_PDAT_FILE"
       *  Add "select ADD_FSP_RAW_BIN"
       *  Add "select ADD_RMU_FILE"
    *  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
    *  Place the pdat.bin files in the location specified by
       CONFIG_FSP_PDAT_FILE
    *  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
    *  Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
       UEFIPAYLOAD.fd
    *  Testing is successful when CorebootPayloadPkg is able to properly
       initialize the serial port without using built-in values.
    
    Change-Id: Ieb6453b045d84702b8f730988d0fed9f253f63e2
    Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
    Reviewed-on: https://review.coreboot.org/14611
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martinroth at google.com>


See https://review.coreboot.org/14611 for details.

-gerrit