[coreboot-gerrit] Patch merged into coreboot/master: rockchip: rk3399: add functions to configure ddrc freq

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit ce60d5a1398d62fa357f4daed3d5d5f4bdfae67e
Author: Shunqian Zheng <zhengsq at rock-chips.com>
Date:   Thu Apr 21 23:53:08 2016 +0800

    rockchip: rk3399: add functions to configure ddrc freq
    
    This patch list four frequencies for ddr controller,
    200MHz, 300MHz, 666MHz and 800MHz and configure
    each freq by setting the DPLL dividers.
    
    By default, the clk_ddrc is from DPLL and equals to DPLL,
    so here we only need to set the DPLL clock.
    
    BRANCH=none
    BUG=chrome-os-partner:51537
    TEST=emerge-kevin coreboot
    
    Change-Id: Ifabe85b5dc95e3c8e3e9cbf946e12e8b06b881cf
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 18ec4f7d8738472fbadd60fa3c8f810f5347ffa2
    Original-Change-Id: I448057542c3885068ddffa5b37d0341ee3ec04b1
    Original-Signed-off-by: Shunqian Zheng <zhengsq at rock-chips.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/340184
    Original-Commit-Ready: Vadim Bendebury <vbendeb at chromium.org>
    Original-Tested-by: Vadim Bendebury <vbendeb at chromium.org>
    Original-Reviewed-by: Vadim Bendebury <vbendeb at chromium.org>
    Reviewed-on: https://review.coreboot.org/14707
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


See https://review.coreboot.org/14707 for details.

-gerrit