[coreboot-gerrit] Patch set updated for coreboot: rockchip: move vop driver from rk3288 to rockchip common
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Sat May 7 09:03:24 CEST 2016
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14731
-gerrit
commit 84901bdff218b30d54ca435d30a1b4d604178593
Author: Shunqian Zheng <zhengsq at rock-chips.com>
Date: Mon May 2 21:38:00 2016 +0800
rockchip: move vop driver from rk3288 to rockchip common
The rk3288 and rk3399 can use a common driver even that
there are some different registers.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=boot from veyron_jerry and check display
Change-Id: I510f68ba00308e47608d6e9921154a5c66ad8858
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: 1d857a7aa68d831a5007210255b121fed7a9e8de
Original-Change-Id: I063e3eebc836debc01c450d8ab9f1524c9a47c56
Original-Signed-off-by: Shunqian Zheng <zhengsq at rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/341633
Original-Reviewed-by: Vadim Bendebury <vbendeb at chromium.org>
Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
---
src/soc/rockchip/common/include/soc/vop.h | 380 ++++++++++++++++++++++++++++++
src/soc/rockchip/common/vop.c | 154 ++++++++++++
src/soc/rockchip/rk3288/Makefile.inc | 2 +-
src/soc/rockchip/rk3288/include/soc/vop.h | 364 ----------------------------
src/soc/rockchip/rk3288/vop.c | 150 ------------
5 files changed, 535 insertions(+), 515 deletions(-)
diff --git a/src/soc/rockchip/common/include/soc/vop.h b/src/soc/rockchip/common/include/soc/vop.h
new file mode 100644
index 0000000..f5ce431
--- /dev/null
+++ b/src/soc/rockchip/common/include/soc/vop.h
@@ -0,0 +1,380 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _ROCKCHIP_LCD_H_
+#define _ROCKCHIP_LCD_H_
+#include <stdint.h>
+#include <edid.h>
+
+struct rockchip_vop_regs {
+ u32 reg_cfg_done;
+ u32 version_info;
+ u32 sys_ctrl;
+ u32 sys_ctrl1;
+ u32 dsp_ctrl0;
+ u32 dsp_ctrl1;
+ u32 dsp_bg;
+ u32 mcu_ctrl;
+ union {
+ u32 intr_ctrl0; /* RK3288 */
+ u32 wb_ctrl0; /* RK3399 */
+ };
+ union {
+ u32 intr_ctrl1; /* RK3288 */
+ u32 wb_ctrl1; /* RK3399 */
+ };
+ union {
+ u32 intr_reserved0; /* RK3288 */
+ u32 wb_yrgb_mst; /* RK3399 */
+ };
+ union {
+ u32 intr_reserved1; /* RK3288 */
+ u32 wb_cbr_mst; /* RK3399 */
+ };
+ u32 win0_ctrl0;
+ u32 win0_ctrl1;
+ u32 win0_color_key;
+ u32 win0_vir;
+ u32 win0_yrgb_mst;
+ u32 win0_cbr_mst;
+ u32 win0_act_info;
+ u32 win0_dsp_info;
+ u32 win0_dsp_st;
+ u32 win0_scl_factor_yrgb;
+ u32 win0_scl_factor_cbr;
+ u32 win0_scl_offset;
+ u32 win0_src_alpha_ctrl;
+ u32 win0_dst_alpha_ctrl;
+ u32 win0_fading_ctrl;
+ union {
+ u32 win0_reserved0; /* RK3288 */
+ u32 win0_ctrl2; /* RK3399 */
+ };
+ u32 win1_ctrl0;
+ u32 win1_ctrl1;
+ u32 win1_color_key;
+ u32 win1_vir;
+ u32 win1_yrgb_mst;
+ u32 win1_cbr_mst;
+ u32 win1_act_info;
+ u32 win1_dsp_info;
+ u32 win1_dsp_st;
+ u32 win1_scl_factor_yrgb;
+ u32 win1_scl_factor_cbr;
+ u32 win1_scl_offset;
+ u32 win1_src_alpha_ctrl;
+ u32 win1_dst_alpha_ctrl;
+ u32 win1_fading_ctrl;
+ union {
+ u32 win1_reservd0; /* RK3288 */
+ u32 win1_ctrl2; /* RK3399 */
+ };
+ u32 reserved2[48];
+ u32 post_dsp_hact_info;
+ u32 post_dsp_vact_info;
+ u32 post_scl_factor_yrgb;
+ u32 post_reserved;
+ u32 post_scl_ctrl;
+ u32 post_dsp_vact_info_f1;
+ u32 dsp_htotal_hs_end;
+ u32 dsp_hact_st_end;
+ u32 dsp_vtotal_vs_end;
+ u32 dsp_vact_st_end;
+ u32 dsp_vs_st_end_f1;
+ u32 dsp_vact_st_end_f1;
+};
+check_member(rockchip_vop_regs, dsp_vact_st_end_f1, 0x19c);
+
+enum rockchip_fb_data_format_t {
+ ARGB8888 = 0,
+ RGB888 = 1,
+ RGB565 = 2,
+};
+
+enum {
+ LB_YUV_3840X5 = 0x0,
+ LB_YUV_2560X8 = 0x1,
+ LB_RGB_3840X2 = 0x2,
+ LB_RGB_2560X4 = 0x3,
+ LB_RGB_1920X5 = 0x4,
+ LB_RGB_1280X8 = 0x5
+};
+
+enum vop_modes {
+ /* EDP == 0 is used for most RK3288 products and is the most likely
+ * use case for RK3399, so keep it as the default. Other desired
+ * modes should be set explicitly in the board's devicetree.cb.
+ */
+ VOP_MODE_EDP = 0,
+ VOP_MODE_HDMI,
+ VOP_MODE_NONE,
+ VOP_MODE_AUTO_DETECT,
+ VOP_MODE_UNKNOWN,
+};
+
+/* VOP_VERSION_INFO */
+#define M_FPGA_VERSION (0xffff << 16)
+#define M_RTL_VERSION (0xffff)
+
+/* VOP_SYS_CTRL */
+#define M_AUTO_GATING_EN (1 << 23)
+#define M_STANDBY_EN (1 << 22)
+#define M_DMA_STOP (1 << 21)
+#define M_MMU_EN (1 << 20)
+#define M_DAM_BURST_LENGTH (0x3 << 18)
+#define M_MIPI_OUT_EN (1 << 15)
+#define M_EDP_OUT_EN (1 << 14)
+#define M_HDMI_OUT_EN (1 << 13)
+#define M_RGB_OUT_EN (1 << 12)
+#define M_ALL_OUT_EN (M_MIPI_OUT_EN | M_EDP_OUT_EN | M_HDMI_OUT_EN | M_RGB_OUT_EN)
+#define M_EDPI_WMS_FS (1 << 10)
+#define M_EDPI_WMS_MODE (1 << 9)
+#define M_EDPI_HALT_EN (1 << 8)
+#define M_DOUB_CH_OVERLAP_NUM (0xf << 4)
+#define M_DOUB_CHANNEL_EN (1 << 3)
+#define M_DIRECT_PATH_LAYER_SEL (0x3 << 1)
+#define M_DIRECT_PATH_EN (1)
+
+#define V_AUTO_GATING_EN(x) (((x) & 1) << 23)
+#define V_STANDBY_EN(x) (((x) & 1) << 22)
+#define V_DMA_STOP(x) (((x) & 1) << 21)
+#define V_MMU_EN(x) (((x) & 1) << 20)
+#define V_DMA_BURST_LENGTH(x) (((x) & 3) << 18)
+#define V_MIPI_OUT_EN(x) (((x) & 1) << 15)
+#define V_EDP_OUT_EN(x) (((x) & 1) << 14)
+#define V_HDMI_OUT_EN(x) (((x) & 1) << 13)
+#define V_RGB_OUT_EN(x) (((x) & 1) << 12)
+#define V_EDPI_WMS_FS(x) (((x) & 1) << 10)
+#define V_EDPI_WMS_MODE(x) (((x) & 1) << 9)
+#define V_EDPI_HALT_EN(x) (((x)&1)<<8)
+#define V_DOUB_CH_OVERLAP_NUM(x) (((x) & 0xf) << 4)
+#define V_DOUB_CHANNEL_EN(x) (((x) & 1) << 3)
+#define V_DIRECT_PATH_LAYER_SEL(x) (((x) & 3) << 1)
+#define V_DIRECT_PATH_EN(x) ((x) & 1)
+
+/* VOP_SYS_CTRL1 */
+#define M_AXI_OUTSTANDING_MAX_NUM (0x1f << 13)
+#define M_AXI_MAX_OUTSTANDING_EN (1 << 12)
+#define M_NOC_WIN_QOS (3 << 10)
+#define M_NOC_QOS_EN (1 << 9)
+#define M_NOC_HURRY_THRESHOLD (0x3f << 3)
+#define M_NOC_HURRY_VALUE (0x3 << 1)
+#define M_NOC_HURRY_EN (1)
+
+#define V_AXI_OUTSTANDING_MAX_NUM(x) (((x) & 0x1f) << 13)
+#define V_AXI_MAX_OUTSTANDING_EN(x) (((x) & 1) << 12)
+#define V_NOC_WIN_QOS(x) (((x) & 3) << 10)
+#define V_NOC_QOS_EN(x) (((x) & 1) << 9)
+#define V_NOC_HURRY_THRESHOLD(x) (((x) & 0x3f) << 3)
+#define V_NOC_HURRY_VALUE(x) (((x) & 3) << 1)
+#define V_NOC_HURRY_EN(x) ((x) & 1)
+
+/* VOP_DSP_CTRL0 */
+#define M_DSP_Y_MIR_EN (1 << 23)
+#define M_DSP_X_MIR_EN (1 << 22)
+#define M_DSP_YUV_CLIP (1 << 21)
+#define M_DSP_CCIR656_AVG (1 << 20)
+#define M_DSP_BLACK_EN (1 << 19)
+#define M_DSP_BLANK_EN (1 << 18)
+#define M_DSP_OUT_ZERO (1 << 17)
+#define M_DSP_DUMMY_SWAP (1 << 16)
+#define M_DSP_DELTA_SWAP (1 << 15)
+#define M_DSP_RG_SWAP (1 << 14)
+#define M_DSP_RB_SWAP (1 << 13)
+#define M_DSP_BG_SWAP (1 << 12)
+#define M_DSP_FIELD_POL (1 << 11)
+#define M_DSP_INTERLACE (1 << 10)
+#define M_DSP_DDR_PHASE (1 << 9)
+#define M_DSP_DCLK_DDR (1 << 8)
+#define M_DSP_DCLK_POL (1 << 7)
+#define M_DSP_DEN_POL (1 << 6)
+#define M_DSP_VSYNC_POL (1 << 5)
+#define M_DSP_HSYNC_POL (1 << 4)
+#define M_DSP_OUT_MODE (0xf)
+
+#define V_DSP_Y_MIR_EN(x) (((x) & 1) << 23)
+#define V_DSP_X_MIR_EN(x) (((x) & 1) << 22)
+#define V_DSP_YUV_CLIP(x) (((x) & 1) << 21)
+#define V_DSP_CCIR656_AVG(x) (((x) & 1) << 20)
+#define V_DSP_BLACK_EN(x) (((x) & 1) << 19)
+#define V_DSP_BLANK_EN(x) (((x) & 1) << 18)
+#define V_DSP_OUT_ZERO(x) (((x) & 1) << 17)
+#define V_DSP_DUMMY_SWAP(x) (((x) & 1) << 16)
+#define V_DSP_DELTA_SWAP(x) (((x) & 1) << 15)
+#define V_DSP_RG_SWAP(x) (((x) & 1) << 14)
+#define V_DSP_RB_SWAP(x) (((x) & 1) << 13)
+#define V_DSP_BG_SWAP(x) (((x) & 1) << 12)
+#define V_DSP_FIELD_POL(x) (((x) & 1) << 11)
+#define V_DSP_INTERLACE(x) (((x) & 1) << 10)
+#define V_DSP_DDR_PHASE(x) (((x) & 1) << 9)
+#define V_DSP_DCLK_DDR(x) (((x) & 1) << 8)
+#define V_DSP_DCLK_POL(x) (((x) & 1) << 7)
+#define V_DSP_DEN_POL(x) (((x) & 1) << 6)
+#define V_DSP_VSYNC_POL(x) (((x) & 1) << 5)
+#define V_DSP_HSYNC_POL(x) (((x) & 1) << 4)
+#define V_DSP_OUT_MODE(x) ((x) & 0xf)
+
+/* VOP_DSP_CTRL1 */
+#define M_DSP_LAYER3_SEL (3 << 14)
+#define M_DSP_LAYER2_SEL (3 << 12)
+#define M_DSP_LAYER1_SEL (3 << 10)
+#define M_DSP_LAYER0_SEL (3 << 8)
+#define M_DITHER_UP_EN (1 << 6)
+#define M_DITHER_DOWN_SEL (1 << 4)
+#define M_DITHER_DOWN_MODE (1 << 3)
+#define M_DITHER_DOWN_EN (1 << 2)
+#define M_PRE_DITHER_DOWN_EN (1 << 1)
+#define M_DSP_LUT_EN (1)
+
+#define V_DSP_LAYER3_SEL(x) (((x) & 3) << 14)
+#define V_DSP_LAYER2_SEL(x) (((x) & 3) << 12)
+#define V_DSP_LAYER1_SEL(x) (((x) & 3) << 10)
+#define V_DSP_LAYER0_SEL(x) (((x) & 3) << 8)
+#define V_DITHER_UP_EN(x) (((x) & 1) << 6)
+#define V_DITHER_DOWN_SEL(x) (((x) & 1) << 4)
+#define V_DITHER_DOWN_MODE(x) (((x) & 1) << 3)
+#define V_DITHER_DOWN_EN(x) (((x) & 1) << 2)
+#define V_PRE_DITHER_DOWN_EN(x) (((x) & 1) << 1)
+#define V_DSP_LUT_EN(x) ((x)&1)
+
+/* VOP_DSP_BG */
+#define M_DSP_BG_RED (0x3f << 20)
+#define M_DSP_BG_GREEN (0x3f << 10)
+#define M_DSP_BG_BLUE (0x3f << 0)
+
+#define V_DSP_BG_RED(x) (((x) & 0x3f) << 20)
+#define V_DSP_BG_GREEN(x) (((x) & 0x3f) << 10)
+#define V_DSP_BG_BLUE(x) (((x) & 0x3f) << 0)
+
+/* VOP_WIN0_CTRL0 */
+#define M_WIN0_YUV_CLIP (1 << 20)
+#define M_WIN0_CBR_DEFLICK (1 << 19)
+#define M_WIN0_YRGB_DEFLICK (1 << 18)
+#define M_WIN0_PPAS_ZERO_EN (1 << 16)
+#define M_WIN0_UV_SWAP (1 << 15)
+#define M_WIN0_MID_SWAP (1 << 14)
+#define M_WIN0_ALPHA_SWAP (1 << 13)
+#define M_WIN0_RB_SWAP (1 << 12)
+#define M_WIN0_CSC_MODE (3 << 10)
+#define M_WIN0_NO_OUTSTANDING (1 << 9)
+#define M_WIN0_INTERLACE_READ (1 << 8)
+#define M_WIN0_LB_MODE (7 << 5)
+#define M_WIN0_FMT_10 (1 << 4)
+#define M_WIN0_DATA_FMT (7 << 1)
+#define M_WIN0_EN (1 << 0)
+
+#define V_WIN0_YUV_CLIP(x) (((x) & 1) << 20)
+#define V_WIN0_CBR_DEFLICK(x) (((x) & 1) << 19)
+#define V_WIN0_YRGB_DEFLICK(x) (((x) & 1) << 18)
+#define V_WIN0_PPAS_ZERO_EN(x) (((x) & 1) << 16)
+#define V_WIN0_UV_SWAP(x) (((x) & 1) << 15)
+#define V_WIN0_MID_SWAP(x) (((x) & 1) << 14)
+#define V_WIN0_ALPHA_SWAP(x) (((x) & 1) << 13)
+#define V_WIN0_RB_SWAP(x) (((x) & 1) << 12)
+#define V_WIN0_CSC_MODE(x) (((x) & 3) << 10)
+#define V_WIN0_NO_OUTSTANDING(x) (((x) & 1) << 9)
+#define V_WIN0_INTERLACE_READ(x) (((x) & 1) << 8)
+#define V_WIN0_LB_MODE(x) (((x) & 7) << 5)
+#define V_WIN0_FMT_10(x) (((x) & 1) << 4)
+#define V_WIN0_DATA_FMT(x) (((x) & 7) << 1)
+#define V_WIN0_EN(x) ((x) & 1)
+
+/* VOP_WIN0_CTRL1 */
+#define M_WIN0_CBR_VSD_MODE (1 << 31)
+#define M_WIN0_CBR_VSU_MODE (1 << 30)
+#define M_WIN0_CBR_HSD_MODE (3 << 28)
+#define M_WIN0_CBR_VER_SCL_MODE (3 << 26)
+#define M_WIN0_CBR_HOR_SCL_MODE (3 << 24)
+#define M_WIN0_YRGB_VSD_MODE (1 << 23)
+#define M_WIN0_YRGB_VSU_MODE (1 << 22)
+#define M_WIN0_YRGB_HSD_MODE (3 << 20)
+#define M_WIN0_YRGB_VER_SCL_MODE (3 << 18)
+#define M_WIN0_YRGB_HOR_SCL_MODE (3 << 16)
+#define M_WIN0_LINE_LOAD_MODE (1 << 15)
+#define M_WIN0_CBR_AXI_GATHER_NUM (7 << 12)
+#define M_WIN0_YRGB_AXI_GATHER_NUM (0xf << 8)
+#define M_WIN0_VSD_CBR_GT2 (1 << 7)
+#define M_WIN0_VSD_CBR_GT4 (1 << 6)
+#define M_WIN0_VSD_YRGB_GT2 (1 << 5)
+#define M_WIN0_VSD_YRGB_GT4 (1 << 4)
+#define M_WIN0_BIC_COE_SEL (3 << 2)
+#define M_WIN0_CBR_AXI_GATHER_EN (1 << 1)
+#define M_WIN0_YRGB_AXI_GATHER_EN (1)
+
+#define V_WIN0_CBR_VSD_MODE(x) (((x) & 1) << 31)
+#define V_WIN0_CBR_VSU_MODE(x) (((x) & 1) << 30)
+#define V_WIN0_CBR_HSD_MODE(x) (((x) & 3) << 28)
+#define V_WIN0_CBR_VER_SCL_MODE(x) (((x) & 3) << 26)
+#define V_WIN0_CBR_HOR_SCL_MODE(x) (((x) & 3) << 24)
+#define V_WIN0_YRGB_VSD_MODE(x) (((x) & 1) << 23)
+#define V_WIN0_YRGB_VSU_MODE(x) (((x) & 1) << 22)
+#define V_WIN0_YRGB_HSD_MODE(x) (((x) & 3) << 20)
+#define V_WIN0_YRGB_VER_SCL_MODE(x) (((x) & 3) << 18)
+#define V_WIN0_YRGB_HOR_SCL_MODE(x) (((x) & 3) << 16)
+#define V_WIN0_LINE_LOAD_MODE(x) (((x) & 1) << 15)
+#define V_WIN0_CBR_AXI_GATHER_NUM(x) (((x) & 7) << 12)
+#define V_WIN0_YRGB_AXI_GATHER_NUM(x) (((x) & 0xf) << 8)
+#define V_WIN0_VSD_CBR_GT2(x) (((x) & 1) << 7)
+#define V_WIN0_VSD_CBR_GT4(x) (((x) & 1) << 6)
+#define V_WIN0_VSD_YRGB_GT2(x) (((x) & 1) << 5)
+#define V_WIN0_VSD_YRGB_GT4(x) (((x) & 1) << 4)
+#define V_WIN0_BIC_COE_SEL(x) (((x) & 3) << 2)
+#define V_WIN0_CBR_AXI_GATHER_EN(x) (((x) & 1) << 1)
+#define V_WIN0_YRGB_AXI_GATHER_EN(x) ((x) & 1)
+
+/*VOP_WIN0_COLOR_KEY*/
+#define M_WIN0_KEY_EN (1 << 31)
+#define M_WIN0_KEY_COLOR (0x3fffffff)
+
+#define V_WIN0_KEY_EN(x) (((x) & 1) << 31)
+#define V_WIN0_KEY_COLOR(x) ((x) & 0x3fffffff)
+
+/* VOP_WIN0_VIR */
+#define V_ARGB888_VIRWIDTH(x) (((x) & 0x3fff) << 0)
+#define V_RGB888_VIRWIDTH(x) (((((x * 3) >> 2)+((x) % 3)) & 0x3fff) << 0)
+#define V_RGB565_VIRWIDTH(x) (((x / 2) & 0x3fff) << 0)
+#define YUV_VIRWIDTH(x) (((x / 4) & 0x3fff) << 0)
+
+/* VOP_WIN0_ACT_INFO */
+#define V_ACT_HEIGHT(x) (((x) & 0x1fff) << 16)
+#define V_ACT_WIDTH(x) ((x) & 0x1fff)
+
+/* VOP_WIN0_DSP_INFO */
+#define V_DSP_HEIGHT(x) (((x) & 0xfff) << 16)
+#define V_DSP_WIDTH(x) ((x) & 0xfff)
+
+/* VOP_WIN0_DSP_ST */
+#define V_DSP_YST(x) (((x) & 0x1fff) << 16)
+#define V_DSP_XST(x) ((x) & 0x1fff)
+
+/* VOP_WIN0_SCL_OFFSET */
+#define V_WIN0_VS_OFFSET_CBR(x) (((x) & 0xff) << 24)
+#define V_WIN0_VS_OFFSET_YRGB(x) (((x) & 0xff) << 16)
+#define V_WIN0_HS_OFFSET_CBR(x) (((x) & 0xff) << 8)
+#define V_WIN0_HS_OFFSET_YRGB(x) ((x) & 0xff)
+
+#define V_HSYNC(x) (((x)&0x1fff)<<0) /* hsync pulse width */
+#define V_HORPRD(x) (((x)&0x1fff)<<16) /* horizontal period */
+#define V_VSYNC(x) (((x)&0x1fff)<<0)
+#define V_VERPRD(x) (((x)&0x1fff)<<16)
+
+#define V_HEAP(x) (((x)&0x1fff)<<0)/* horizontal active end */
+#define V_HASP(x) (((x)&0x1fff)<<16)/* horizontal active start */
+#define V_VAEP(x) (((x)&0x1fff)<<0)
+#define V_VASP(x) (((x)&0x1fff)<<16)
+
+void rkvop_mode_set(u32 vop_id, const struct edid *edid, u32 mode);
+void rkvop_enable(u32 vop_id, u32 fbbase, const struct edid *edid);
+#endif
diff --git a/src/soc/rockchip/common/vop.c b/src/soc/rockchip/common/vop.c
new file mode 100644
index 0000000..668bee0
--- /dev/null
+++ b/src/soc/rockchip/common/vop.c
@@ -0,0 +1,154 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <delay.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stddef.h>
+#include <soc/addressmap.h>
+#include <soc/clock.h>
+#include <soc/edp.h>
+#include <soc/vop.h>
+
+
+static struct rockchip_vop_regs * const vop_regs[] = {
+ (struct rockchip_vop_regs *)VOP_BIG_BASE,
+ (struct rockchip_vop_regs *)VOP_LIT_BASE
+};
+
+void rkvop_enable(u32 vop_id, u32 fbbase, const struct edid *edid)
+{
+ u32 lb_mode;
+ u32 rgb_mode;
+ u32 hactive = edid->mode.ha;
+ u32 vactive = edid->mode.va;
+ u32 hsync_len = edid->mode.hspw;
+ u32 hback_porch = edid->mode.hbl - edid->mode.hso - edid->mode.hspw;
+ u32 vsync_len = edid->mode.vspw;
+ u32 vback_porch = edid->mode.vbl - edid->mode.vso - edid->mode.vspw;
+ u32 xpos = 0, ypos = 0;
+ struct rockchip_vop_regs *preg = vop_regs[vop_id];
+
+ write32(&preg->win0_act_info,
+ V_ACT_WIDTH(hactive - 1) | V_ACT_HEIGHT(vactive - 1));
+
+ write32(&preg->win0_dsp_st, V_DSP_XST(xpos + hsync_len + hback_porch) |
+ V_DSP_YST(ypos + vsync_len + vback_porch));
+
+ write32(&preg->win0_dsp_info, V_DSP_WIDTH(hactive - 1) |
+ V_DSP_HEIGHT(vactive - 1));
+
+ clrsetbits_le32(&preg->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR,
+ V_WIN0_KEY_EN(0) |
+ V_WIN0_KEY_COLOR(0));
+
+ switch (edid->framebuffer_bits_per_pixel) {
+ case 16:
+ rgb_mode = RGB565;
+ write32(&preg->win0_vir, V_RGB565_VIRWIDTH(hactive));
+ break;
+ case 24:
+ rgb_mode = RGB888;
+ write32(&preg->win0_vir, V_RGB888_VIRWIDTH(hactive));
+ break;
+ case 32:
+ default:
+ rgb_mode = ARGB8888;
+ write32(&preg->win0_vir, V_ARGB888_VIRWIDTH(hactive));
+ break;
+ }
+
+ if (hactive > 2560)
+ lb_mode = LB_RGB_3840X2;
+ else if (hactive > 1920)
+ lb_mode = LB_RGB_2560X4;
+ else if (hactive > 1280)
+ lb_mode = LB_RGB_1920X5;
+ else
+ lb_mode = LB_RGB_1280X8;
+
+ clrsetbits_le32(&preg->win0_ctrl0,
+ M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN,
+ V_WIN0_LB_MODE(lb_mode) |
+ V_WIN0_DATA_FMT(rgb_mode) | V_WIN0_EN(1));
+
+ write32(&preg->win0_yrgb_mst, fbbase);
+
+ /* On RK3288, the reg_cfg_done[1:31] is reserved and read-only,
+ * but it's fine to write to it
+ */
+ write32(&preg->reg_cfg_done, 0xffff); /* enable reg config */
+}
+
+void rkvop_mode_set(u32 vop_id, const struct edid *edid, u32 mode)
+{
+ u32 hactive = edid->mode.ha;
+ u32 vactive = edid->mode.va;
+ u32 hfront_porch = edid->mode.hso;
+ u32 hsync_len = edid->mode.hspw;
+ u32 hback_porch = edid->mode.hbl - edid->mode.hso - edid->mode.hspw;
+ u32 vfront_porch = edid->mode.vso;
+ u32 vsync_len = edid->mode.vspw;
+ u32 vback_porch = edid->mode.vbl - edid->mode.vso - edid->mode.vspw;
+ struct rockchip_vop_regs *preg = vop_regs[vop_id];
+
+ switch (mode) {
+
+ case VOP_MODE_HDMI:
+ clrsetbits_le32(&preg->sys_ctrl,
+ M_ALL_OUT_EN, V_HDMI_OUT_EN(1));
+ break;
+
+ case VOP_MODE_EDP:
+ default:
+ clrsetbits_le32(&preg->sys_ctrl,
+ M_ALL_OUT_EN, V_EDP_OUT_EN(1));
+ break;
+ }
+ clrsetbits_le32(&preg->dsp_ctrl0,
+ M_DSP_OUT_MODE | M_DSP_VSYNC_POL | M_DSP_HSYNC_POL,
+ V_DSP_OUT_MODE(15) |
+ V_DSP_HSYNC_POL(edid->mode.phsync == '+') |
+ V_DSP_VSYNC_POL(edid->mode.pvsync == '+'));
+
+ write32(&preg->dsp_htotal_hs_end, V_HSYNC(hsync_len) |
+ V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch));
+
+ write32(&preg->dsp_hact_st_end,
+ V_HEAP(hsync_len + hback_porch + hactive) |
+ V_HASP(hsync_len + hback_porch));
+
+ write32(&preg->dsp_vtotal_vs_end, V_VSYNC(vsync_len) |
+ V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch));
+
+ write32(&preg->dsp_vact_st_end,
+ V_VAEP(vsync_len + vback_porch + vactive) |
+ V_VASP(vsync_len + vback_porch));
+
+ write32(&preg->post_dsp_hact_info,
+ V_HEAP(hsync_len + hback_porch + hactive) |
+ V_HASP(hsync_len + hback_porch));
+
+ write32(&preg->post_dsp_vact_info,
+ V_VAEP(vsync_len + vback_porch + vactive) |
+ V_VASP(vsync_len + vback_porch));
+
+ /* On RK3288, the reg_cfg_done[1:31] is reserved and read-only,
+ * but it's fine to write to it
+ */
+ write32(&preg->reg_cfg_done, 0xffff); /* enable reg config */
+}
diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc
index 9d0e9c2..b29038d 100644
--- a/src/soc/rockchip/rk3288/Makefile.inc
+++ b/src/soc/rockchip/rk3288/Makefile.inc
@@ -67,7 +67,7 @@ ramstage-y += ../common/gpio.c
ramstage-y += gpio.c
ramstage-y += ../common/rk808.c
ramstage-y += ../common/pwm.c
-ramstage-y += vop.c
+ramstage-y += ../common/vop.c
ramstage-y += ../common/edp.c
ramstage-y += hdmi.c
ramstage-y += display.c
diff --git a/src/soc/rockchip/rk3288/include/soc/vop.h b/src/soc/rockchip/rk3288/include/soc/vop.h
deleted file mode 100644
index b3cd9ff..0000000
--- a/src/soc/rockchip/rk3288/include/soc/vop.h
+++ /dev/null
@@ -1,364 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _RK3288_LCD_H_
-#define _RK3288_LCD_H_
-#include <stdint.h>
-#include <edid.h>
-
-struct rk3288_vop_regs {
- u32 reg_cfg_done;
- u32 version_info;
- u32 sys_ctrl;
- u32 sys_ctrl1;
- u32 dsp_ctrl0;
- u32 dsp_ctrl1;
- u32 dsp_bg;
- u32 mcu_ctrl;
- u32 intr_ctrl0;
- u32 intr_ctrl1;
- u32 intr_reserved0;
- u32 intr_reserved1;
-
- u32 win0_ctrl0;
- u32 win0_ctrl1;
- u32 win0_color_key;
- u32 win0_vir;
- u32 win0_yrgb_mst;
- u32 win0_cbr_mst;
- u32 win0_act_info;
- u32 win0_dsp_info;
- u32 win0_dsp_st;
- u32 win0_scl_factor_yrgb;
- u32 win0_scl_factor_cbr;
- u32 win0_scl_offset;
- u32 win0_src_alpha_ctrl;
- u32 win0_dst_alpha_ctrl;
- u32 win0_fading_ctrl;
- u32 win0_reserved0;
-
- u32 win1_ctrl0;
- u32 win1_ctrl1;
- u32 win1_color_key;
- u32 win1_vir;
- u32 win1_yrgb_mst;
- u32 win1_cbr_mst;
- u32 win1_act_info;
- u32 win1_dsp_info;
- u32 win1_dsp_st;
- u32 win1_scl_factor_yrgb;
- u32 win1_scl_factor_cbr;
- u32 win1_scl_offset;
- u32 win1_src_alpha_ctrl;
- u32 win1_dst_alpha_ctrl;
- u32 win1_fading_ctrl;
- u32 win1_reservd0;
- u32 reserved2[48];
- u32 post_dsp_hact_info;
- u32 post_dsp_vact_info;
- u32 post_scl_factor_yrgb;
- u32 post_reserved;
- u32 post_scl_ctrl;
- u32 post_dsp_vact_info_f1;
- u32 dsp_htotal_hs_end;
- u32 dsp_hact_st_end;
- u32 dsp_vtotal_vs_end;
- u32 dsp_vact_st_end;
- u32 dsp_vs_st_end_f1;
- u32 dsp_vact_st_end_f1;
-};
-check_member(rk3288_vop_regs, dsp_vact_st_end_f1, 0x19c);
-
-enum rockchip_fb_data_format_t {
- ARGB8888 = 0,
- RGB888 = 1,
- RGB565 = 2,
-};
-
-enum {
- LB_YUV_3840X5 = 0x0,
- LB_YUV_2560X8 = 0x1,
- LB_RGB_3840X2 = 0x2,
- LB_RGB_2560X4 = 0x3,
- LB_RGB_1920X5 = 0x4,
- LB_RGB_1280X8 = 0x5
-};
-
-enum vop_modes {
- /* EDP == 0 is used for early RK3288 products and is the most likely
- * use case, so keep it as the default. Other desired modes should
- * be set explicitly in the board's devicetree.cb.
- */
- VOP_MODE_EDP = 0,
- VOP_MODE_HDMI,
- VOP_MODE_NONE,
- VOP_MODE_AUTO_DETECT,
- VOP_MODE_UNKNOWN,
-};
-
-/* VOP_VERSION_INFO */
-#define M_FPGA_VERSION (0xffff << 16)
-#define M_RTL_VERSION (0xffff)
-
-/* VOP_SYS_CTRL */
-#define M_AUTO_GATING_EN (1 << 23)
-#define M_STANDBY_EN (1 << 22)
-#define M_DMA_STOP (1 << 21)
-#define M_MMU_EN (1 << 20)
-#define M_DAM_BURST_LENGTH (0x3 << 18)
-#define M_MIPI_OUT_EN (1 << 15)
-#define M_EDP_OUT_EN (1 << 14)
-#define M_HDMI_OUT_EN (1 << 13)
-#define M_RGB_OUT_EN (1 << 12)
-#define M_ALL_OUT_EN (M_MIPI_OUT_EN | M_EDP_OUT_EN | M_HDMI_OUT_EN | M_RGB_OUT_EN)
-#define M_EDPI_WMS_FS (1 << 10)
-#define M_EDPI_WMS_MODE (1 << 9)
-#define M_EDPI_HALT_EN (1 << 8)
-#define M_DOUB_CH_OVERLAP_NUM (0xf << 4)
-#define M_DOUB_CHANNEL_EN (1 << 3)
-#define M_DIRECT_PATH_LAYER_SEL (0x3 << 1)
-#define M_DIRECT_PATH_EN (1)
-
-#define V_AUTO_GATING_EN(x) (((x) & 1) << 23)
-#define V_STANDBY_EN(x) (((x) & 1) << 22)
-#define V_DMA_STOP(x) (((x) & 1) << 21)
-#define V_MMU_EN(x) (((x) & 1) << 20)
-#define V_DMA_BURST_LENGTH(x) (((x) & 3) << 18)
-#define V_MIPI_OUT_EN(x) (((x) & 1) << 15)
-#define V_EDP_OUT_EN(x) (((x) & 1) << 14)
-#define V_HDMI_OUT_EN(x) (((x) & 1) << 13)
-#define V_RGB_OUT_EN(x) (((x) & 1) << 12)
-#define V_EDPI_WMS_FS(x) (((x) & 1) << 10)
-#define V_EDPI_WMS_MODE(x) (((x) & 1) << 9)
-#define V_EDPI_HALT_EN(x) (((x)&1)<<8)
-#define V_DOUB_CH_OVERLAP_NUM(x) (((x) & 0xf) << 4)
-#define V_DOUB_CHANNEL_EN(x) (((x) & 1) << 3)
-#define V_DIRECT_PATH_LAYER_SEL(x) (((x) & 3) << 1)
-#define V_DIRECT_PATH_EN(x) ((x) & 1)
-
-/* VOP_SYS_CTRL1 */
-#define M_AXI_OUTSTANDING_MAX_NUM (0x1f << 13)
-#define M_AXI_MAX_OUTSTANDING_EN (1 << 12)
-#define M_NOC_WIN_QOS (3 << 10)
-#define M_NOC_QOS_EN (1 << 9)
-#define M_NOC_HURRY_THRESHOLD (0x3f << 3)
-#define M_NOC_HURRY_VALUE (0x3 << 1)
-#define M_NOC_HURRY_EN (1)
-
-#define V_AXI_OUTSTANDING_MAX_NUM(x) (((x) & 0x1f) << 13)
-#define V_AXI_MAX_OUTSTANDING_EN(x) (((x) & 1) << 12)
-#define V_NOC_WIN_QOS(x) (((x) & 3) << 10)
-#define V_NOC_QOS_EN(x) (((x) & 1) << 9)
-#define V_NOC_HURRY_THRESHOLD(x) (((x) & 0x3f) << 3)
-#define V_NOC_HURRY_VALUE(x) (((x) & 3) << 1)
-#define V_NOC_HURRY_EN(x) ((x) & 1)
-
-/* VOP_DSP_CTRL0 */
-#define M_DSP_Y_MIR_EN (1 << 23)
-#define M_DSP_X_MIR_EN (1 << 22)
-#define M_DSP_YUV_CLIP (1 << 21)
-#define M_DSP_CCIR656_AVG (1 << 20)
-#define M_DSP_BLACK_EN (1 << 19)
-#define M_DSP_BLANK_EN (1 << 18)
-#define M_DSP_OUT_ZERO (1 << 17)
-#define M_DSP_DUMMY_SWAP (1 << 16)
-#define M_DSP_DELTA_SWAP (1 << 15)
-#define M_DSP_RG_SWAP (1 << 14)
-#define M_DSP_RB_SWAP (1 << 13)
-#define M_DSP_BG_SWAP (1 << 12)
-#define M_DSP_FIELD_POL (1 << 11)
-#define M_DSP_INTERLACE (1 << 10)
-#define M_DSP_DDR_PHASE (1 << 9)
-#define M_DSP_DCLK_DDR (1 << 8)
-#define M_DSP_DCLK_POL (1 << 7)
-#define M_DSP_DEN_POL (1 << 6)
-#define M_DSP_VSYNC_POL (1 << 5)
-#define M_DSP_HSYNC_POL (1 << 4)
-#define M_DSP_OUT_MODE (0xf)
-
-#define V_DSP_Y_MIR_EN(x) (((x) & 1) << 23)
-#define V_DSP_X_MIR_EN(x) (((x) & 1) << 22)
-#define V_DSP_YUV_CLIP(x) (((x) & 1) << 21)
-#define V_DSP_CCIR656_AVG(x) (((x) & 1) << 20)
-#define V_DSP_BLACK_EN(x) (((x) & 1) << 19)
-#define V_DSP_BLANK_EN(x) (((x) & 1) << 18)
-#define V_DSP_OUT_ZERO(x) (((x) & 1) << 17)
-#define V_DSP_DUMMY_SWAP(x) (((x) & 1) << 16)
-#define V_DSP_DELTA_SWAP(x) (((x) & 1) << 15)
-#define V_DSP_RG_SWAP(x) (((x) & 1) << 14)
-#define V_DSP_RB_SWAP(x) (((x) & 1) << 13)
-#define V_DSP_BG_SWAP(x) (((x) & 1) << 12)
-#define V_DSP_FIELD_POL(x) (((x) & 1) << 11)
-#define V_DSP_INTERLACE(x) (((x) & 1) << 10)
-#define V_DSP_DDR_PHASE(x) (((x) & 1) << 9)
-#define V_DSP_DCLK_DDR(x) (((x) & 1) << 8)
-#define V_DSP_DCLK_POL(x) (((x) & 1) << 7)
-#define V_DSP_DEN_POL(x) (((x) & 1) << 6)
-#define V_DSP_VSYNC_POL(x) (((x) & 1) << 5)
-#define V_DSP_HSYNC_POL(x) (((x) & 1) << 4)
-#define V_DSP_OUT_MODE(x) ((x) & 0xf)
-
-/* VOP_DSP_CTRL1 */
-#define M_DSP_LAYER3_SEL (3 << 14)
-#define M_DSP_LAYER2_SEL (3 << 12)
-#define M_DSP_LAYER1_SEL (3 << 10)
-#define M_DSP_LAYER0_SEL (3 << 8)
-#define M_DITHER_UP_EN (1 << 6)
-#define M_DITHER_DOWN_SEL (1 << 4)
-#define M_DITHER_DOWN_MODE (1 << 3)
-#define M_DITHER_DOWN_EN (1 << 2)
-#define M_PRE_DITHER_DOWN_EN (1 << 1)
-#define M_DSP_LUT_EN (1)
-
-#define V_DSP_LAYER3_SEL(x) (((x) & 3) << 14)
-#define V_DSP_LAYER2_SEL(x) (((x) & 3) << 12)
-#define V_DSP_LAYER1_SEL(x) (((x) & 3) << 10)
-#define V_DSP_LAYER0_SEL(x) (((x) & 3) << 8)
-#define V_DITHER_UP_EN(x) (((x) & 1) << 6)
-#define V_DITHER_DOWN_SEL(x) (((x) & 1) << 4)
-#define V_DITHER_DOWN_MODE(x) (((x) & 1) << 3)
-#define V_DITHER_DOWN_EN(x) (((x) & 1) << 2)
-#define V_PRE_DITHER_DOWN_EN(x) (((x) & 1) << 1)
-#define V_DSP_LUT_EN(x) ((x)&1)
-
-/* VOP_DSP_BG */
-#define M_DSP_BG_RED (0x3f << 20)
-#define M_DSP_BG_GREEN (0x3f << 10)
-#define M_DSP_BG_BLUE (0x3f << 0)
-
-#define V_DSP_BG_RED(x) (((x) & 0x3f) << 20)
-#define V_DSP_BG_GREEN(x) (((x) & 0x3f) << 10)
-#define V_DSP_BG_BLUE(x) (((x) & 0x3f) << 0)
-
-/* VOP_WIN0_CTRL0 */
-#define M_WIN0_YUV_CLIP (1 << 20)
-#define M_WIN0_CBR_DEFLICK (1 << 19)
-#define M_WIN0_YRGB_DEFLICK (1 << 18)
-#define M_WIN0_PPAS_ZERO_EN (1 << 16)
-#define M_WIN0_UV_SWAP (1 << 15)
-#define M_WIN0_MID_SWAP (1 << 14)
-#define M_WIN0_ALPHA_SWAP (1 << 13)
-#define M_WIN0_RB_SWAP (1 << 12)
-#define M_WIN0_CSC_MODE (3 << 10)
-#define M_WIN0_NO_OUTSTANDING (1 << 9)
-#define M_WIN0_INTERLACE_READ (1 << 8)
-#define M_WIN0_LB_MODE (7 << 5)
-#define M_WIN0_FMT_10 (1 << 4)
-#define M_WIN0_DATA_FMT (7 << 1)
-#define M_WIN0_EN (1 << 0)
-
-#define V_WIN0_YUV_CLIP(x) (((x) & 1) << 20)
-#define V_WIN0_CBR_DEFLICK(x) (((x) & 1) << 19)
-#define V_WIN0_YRGB_DEFLICK(x) (((x) & 1) << 18)
-#define V_WIN0_PPAS_ZERO_EN(x) (((x) & 1) << 16)
-#define V_WIN0_UV_SWAP(x) (((x) & 1) << 15)
-#define V_WIN0_MID_SWAP(x) (((x) & 1) << 14)
-#define V_WIN0_ALPHA_SWAP(x) (((x) & 1) << 13)
-#define V_WIN0_RB_SWAP(x) (((x) & 1) << 12)
-#define V_WIN0_CSC_MODE(x) (((x) & 3) << 10)
-#define V_WIN0_NO_OUTSTANDING(x) (((x) & 1) << 9)
-#define V_WIN0_INTERLACE_READ(x) (((x) & 1) << 8)
-#define V_WIN0_LB_MODE(x) (((x) & 7) << 5)
-#define V_WIN0_FMT_10(x) (((x) & 1) << 4)
-#define V_WIN0_DATA_FMT(x) (((x) & 7) << 1)
-#define V_WIN0_EN(x) ((x) & 1)
-
-/* VOP_WIN0_CTRL1 */
-#define M_WIN0_CBR_VSD_MODE (1 << 31)
-#define M_WIN0_CBR_VSU_MODE (1 << 30)
-#define M_WIN0_CBR_HSD_MODE (3 << 28)
-#define M_WIN0_CBR_VER_SCL_MODE (3 << 26)
-#define M_WIN0_CBR_HOR_SCL_MODE (3 << 24)
-#define M_WIN0_YRGB_VSD_MODE (1 << 23)
-#define M_WIN0_YRGB_VSU_MODE (1 << 22)
-#define M_WIN0_YRGB_HSD_MODE (3 << 20)
-#define M_WIN0_YRGB_VER_SCL_MODE (3 << 18)
-#define M_WIN0_YRGB_HOR_SCL_MODE (3 << 16)
-#define M_WIN0_LINE_LOAD_MODE (1 << 15)
-#define M_WIN0_CBR_AXI_GATHER_NUM (7 << 12)
-#define M_WIN0_YRGB_AXI_GATHER_NUM (0xf << 8)
-#define M_WIN0_VSD_CBR_GT2 (1 << 7)
-#define M_WIN0_VSD_CBR_GT4 (1 << 6)
-#define M_WIN0_VSD_YRGB_GT2 (1 << 5)
-#define M_WIN0_VSD_YRGB_GT4 (1 << 4)
-#define M_WIN0_BIC_COE_SEL (3 << 2)
-#define M_WIN0_CBR_AXI_GATHER_EN (1 << 1)
-#define M_WIN0_YRGB_AXI_GATHER_EN (1)
-
-#define V_WIN0_CBR_VSD_MODE(x) (((x) & 1) << 31)
-#define V_WIN0_CBR_VSU_MODE(x) (((x) & 1) << 30)
-#define V_WIN0_CBR_HSD_MODE(x) (((x) & 3) << 28)
-#define V_WIN0_CBR_VER_SCL_MODE(x) (((x) & 3) << 26)
-#define V_WIN0_CBR_HOR_SCL_MODE(x) (((x) & 3) << 24)
-#define V_WIN0_YRGB_VSD_MODE(x) (((x) & 1) << 23)
-#define V_WIN0_YRGB_VSU_MODE(x) (((x) & 1) << 22)
-#define V_WIN0_YRGB_HSD_MODE(x) (((x) & 3) << 20)
-#define V_WIN0_YRGB_VER_SCL_MODE(x) (((x) & 3) << 18)
-#define V_WIN0_YRGB_HOR_SCL_MODE(x) (((x) & 3) << 16)
-#define V_WIN0_LINE_LOAD_MODE(x) (((x) & 1) << 15)
-#define V_WIN0_CBR_AXI_GATHER_NUM(x) (((x) & 7) << 12)
-#define V_WIN0_YRGB_AXI_GATHER_NUM(x) (((x) & 0xf) << 8)
-#define V_WIN0_VSD_CBR_GT2(x) (((x) & 1) << 7)
-#define V_WIN0_VSD_CBR_GT4(x) (((x) & 1) << 6)
-#define V_WIN0_VSD_YRGB_GT2(x) (((x) & 1) << 5)
-#define V_WIN0_VSD_YRGB_GT4(x) (((x) & 1) << 4)
-#define V_WIN0_BIC_COE_SEL(x) (((x) & 3) << 2)
-#define V_WIN0_CBR_AXI_GATHER_EN(x) (((x) & 1) << 1)
-#define V_WIN0_YRGB_AXI_GATHER_EN(x) ((x) & 1)
-
-/*VOP_WIN0_COLOR_KEY*/
-#define M_WIN0_KEY_EN (1 << 31)
-#define M_WIN0_KEY_COLOR (0x3fffffff)
-
-#define V_WIN0_KEY_EN(x) (((x) & 1) << 31)
-#define V_WIN0_KEY_COLOR(x) ((x) & 0x3fffffff)
-
-/* VOP_WIN0_VIR */
-#define V_ARGB888_VIRWIDTH(x) (((x) & 0x3fff) << 0)
-#define V_RGB888_VIRWIDTH(x) (((((x * 3) >> 2)+((x) % 3)) & 0x3fff) << 0)
-#define V_RGB565_VIRWIDTH(x) (((x / 2) & 0x3fff) << 0)
-#define YUV_VIRWIDTH(x) (((x / 4) & 0x3fff) << 0)
-
-/* VOP_WIN0_ACT_INFO */
-#define V_ACT_HEIGHT(x) (((x) & 0x1fff) << 16)
-#define V_ACT_WIDTH(x) ((x) & 0x1fff)
-
-/* VOP_WIN0_DSP_INFO */
-#define V_DSP_HEIGHT(x) (((x) & 0xfff) << 16)
-#define V_DSP_WIDTH(x) ((x) & 0xfff)
-
-/* VOP_WIN0_DSP_ST */
-#define V_DSP_YST(x) (((x) & 0x1fff) << 16)
-#define V_DSP_XST(x) ((x) & 0x1fff)
-
-/* VOP_WIN0_SCL_OFFSET */
-#define V_WIN0_VS_OFFSET_CBR(x) (((x) & 0xff) << 24)
-#define V_WIN0_VS_OFFSET_YRGB(x) (((x) & 0xff) << 16)
-#define V_WIN0_HS_OFFSET_CBR(x) (((x) & 0xff) << 8)
-#define V_WIN0_HS_OFFSET_YRGB(x) ((x) & 0xff)
-
-#define V_HSYNC(x) (((x)&0x1fff)<<0) /* hsync pulse width */
-#define V_HORPRD(x) (((x)&0x1fff)<<16) /* horizontal period */
-#define V_VSYNC(x) (((x)&0x1fff)<<0)
-#define V_VERPRD(x) (((x)&0x1fff)<<16)
-
-#define V_HEAP(x) (((x)&0x1fff)<<0)/* horizontal active end */
-#define V_HASP(x) (((x)&0x1fff)<<16)/* horizontal active start */
-#define V_VAEP(x) (((x)&0x1fff)<<0)
-#define V_VASP(x) (((x)&0x1fff)<<16)
-
-void rkvop_mode_set(u32 vop_id, const struct edid *edid, u32 mode);
-void rkvop_enable(u32 vop_id, u32 fbbase, const struct edid *edid);
-#endif
diff --git a/src/soc/rockchip/rk3288/vop.c b/src/soc/rockchip/rk3288/vop.c
deleted file mode 100644
index 607cf8f..0000000
--- a/src/soc/rockchip/rk3288/vop.c
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <console/console.h>
-#include <delay.h>
-#include <stdlib.h>
-#include <string.h>
-#include <stddef.h>
-#include <soc/addressmap.h>
-#include <soc/clock.h>
-#include <soc/edp.h>
-#include <soc/vop.h>
-
-#include "chip.h"
-
-static struct rk3288_vop_regs * const vop_regs[] = {
- (struct rk3288_vop_regs *)VOP_BIG_BASE,
- (struct rk3288_vop_regs *)VOP_LIT_BASE
-};
-
-void rkvop_enable(u32 vop_id, u32 fbbase, const struct edid *edid)
-{
- u32 lb_mode;
- u32 rgb_mode;
- u32 hactive = edid->mode.ha;
- u32 vactive = edid->mode.va;
- u32 hsync_len = edid->mode.hspw;
- u32 hback_porch = edid->mode.hbl - edid->mode.hso - edid->mode.hspw;
- u32 vsync_len = edid->mode.vspw;
- u32 vback_porch = edid->mode.vbl - edid->mode.vso - edid->mode.vspw;
- u32 xpos = 0, ypos = 0;
- struct rk3288_vop_regs *preg = vop_regs[vop_id];
-
- write32(&preg->win0_act_info,
- V_ACT_WIDTH(hactive - 1) | V_ACT_HEIGHT(vactive - 1));
-
- write32(&preg->win0_dsp_st, V_DSP_XST(xpos + hsync_len + hback_porch) |
- V_DSP_YST(ypos + vsync_len + vback_porch));
-
- write32(&preg->win0_dsp_info, V_DSP_WIDTH(hactive - 1) |
- V_DSP_HEIGHT(vactive - 1));
-
- clrsetbits_le32(&preg->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR,
- V_WIN0_KEY_EN(0) |
- V_WIN0_KEY_COLOR(0));
-
- switch (edid->framebuffer_bits_per_pixel) {
- case 16:
- rgb_mode = RGB565;
- write32(&preg->win0_vir, V_RGB565_VIRWIDTH(hactive));
- break;
- case 24:
- rgb_mode = RGB888;
- write32(&preg->win0_vir, V_RGB888_VIRWIDTH(hactive));
- break;
- case 32:
- default:
- rgb_mode = ARGB8888;
- write32(&preg->win0_vir, V_ARGB888_VIRWIDTH(hactive));
- break;
- }
-
- if (hactive > 2560)
- lb_mode = LB_RGB_3840X2;
- else if (hactive > 1920)
- lb_mode = LB_RGB_2560X4;
- else if (hactive > 1280)
- lb_mode = LB_RGB_1920X5;
- else
- lb_mode = LB_RGB_1280X8;
-
- clrsetbits_le32(&preg->win0_ctrl0,
- M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN,
- V_WIN0_LB_MODE(lb_mode) |
- V_WIN0_DATA_FMT(rgb_mode) | V_WIN0_EN(1));
-
- write32(&preg->win0_yrgb_mst, fbbase);
-
- write32(&preg->reg_cfg_done, 0x01); /* enable reg config */
-}
-
-void rkvop_mode_set(u32 vop_id, const struct edid *edid, u32 mode)
-{
- u32 hactive = edid->mode.ha;
- u32 vactive = edid->mode.va;
- u32 hfront_porch = edid->mode.hso;
- u32 hsync_len = edid->mode.hspw;
- u32 hback_porch = edid->mode.hbl - edid->mode.hso - edid->mode.hspw;
- u32 vfront_porch = edid->mode.vso;
- u32 vsync_len = edid->mode.vspw;
- u32 vback_porch = edid->mode.vbl - edid->mode.vso - edid->mode.vspw;
- struct rk3288_vop_regs *preg = vop_regs[vop_id];
-
- switch (mode) {
-
- case VOP_MODE_HDMI:
- clrsetbits_le32(&preg->sys_ctrl,
- M_ALL_OUT_EN, V_HDMI_OUT_EN(1));
- break;
-
- case VOP_MODE_EDP:
- default:
- clrsetbits_le32(&preg->sys_ctrl,
- M_ALL_OUT_EN, V_EDP_OUT_EN(1));
- break;
- }
-
- clrsetbits_le32(&preg->dsp_ctrl0,
- M_DSP_OUT_MODE | M_DSP_VSYNC_POL | M_DSP_HSYNC_POL,
- V_DSP_OUT_MODE(15) |
- V_DSP_HSYNC_POL(edid->mode.phsync == '+') |
- V_DSP_VSYNC_POL(edid->mode.pvsync == '+'));
-
- write32(&preg->dsp_htotal_hs_end, V_HSYNC(hsync_len) |
- V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch));
-
- write32(&preg->dsp_hact_st_end,
- V_HEAP(hsync_len + hback_porch + hactive) |
- V_HASP(hsync_len + hback_porch));
-
- write32(&preg->dsp_vtotal_vs_end, V_VSYNC(vsync_len) |
- V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch));
-
- write32(&preg->dsp_vact_st_end,
- V_VAEP(vsync_len + vback_porch + vactive) |
- V_VASP(vsync_len + vback_porch));
-
- write32(&preg->post_dsp_hact_info,
- V_HEAP(hsync_len + hback_porch + hactive) |
- V_HASP(hsync_len + hback_porch));
-
- write32(&preg->post_dsp_vact_info,
- V_VAEP(vsync_len + vback_porch + vactive) |
- V_VASP(vsync_len + vback_porch));
-
- write32(&preg->reg_cfg_done, 0x01); /* enable reg config */
-}
More information about the coreboot-gerrit
mailing list