[coreboot-gerrit] New patch to review for coreboot: google/oak: elm: Do not control SPI_LEVEL_ENABLE after elm-rev1

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14694

-gerrit

commit f479892d182dc86d846f9a04b713e397c0b6c9fb
Author: Yidi Lin <yidi.lin at mediatek.com>
Date:   Wed Apr 6 16:28:06 2016 +0800

    google/oak: elm: Do not control SPI_LEVEL_ENABLE after elm-rev1
    
    SPI level shifter is controlled by SRCLKENA0 after elm-rev1.
    We don't need to configure it in the bootloader.
    
    BUG=chrome-os-partner:51725
    TEST=emerge-elm coreboot
    
    Change-Id: I01ec00965b87ae370b72d3c0521fb37268714cf8
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 3234065e33c46bc2d67a96939422d318919d5e7a
    Original-Change-Id: Iafed0cd7562eb5921af6b17f73a067d469143e02
    Original-Signed-off-by: Yidi Lin <yidi.lin at mediatek.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/337421
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
---
 src/mainboard/google/oak/bootblock.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c
index 325889c..04a3a55 100644
--- a/src/mainboard/google/oak/bootblock.c
+++ b/src/mainboard/google/oak/bootblock.c
@@ -81,7 +81,8 @@ void bootblock_mainboard_init(void)
 	nor_set_gpio_pinmux();
 
 	/* SPI_LEVEL_ENABLE: Enable 1.8V to 3.3V level shifter for EC SPI bus */
-	if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 4)
+	if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 4 &&
+	    board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 8)
 		gpio_output(PAD_SRCLKENAI2, 1);
 
 	/* Init i2c bus 2 Timing register for TPM */