[coreboot-gerrit] New patch to review for coreboot: x86: Remove ramstage cache
Furquan Shaikh (furquan@google.com)
gerrit at coreboot.org
Fri May 6 08:24:56 CEST 2016
Furquan Shaikh (furquan at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14631
-gerrit
commit 8478204ed6a9556423d5b4729b64573d5b30f6f3
Author: Furquan Shaikh <furquan at google.com>
Date: Thu May 5 22:06:43 2016 -0700
x86: Remove ramstage cache
Before multi-CBFS support was added, x86 platforms cached their
ramstage in TSEG so that it could be re-used on the resume
path. However, more resources/assets are being put in cbfs that are
utilized during ramstage. Just caching ramstage does not mean that
correct cbfs region is used for all the data. Thus, instead of caching
ramstage for resume, utilize whatever is present in the CBFS region that
we are using.
Change-Id: Ib5dbc8303b641c97aabd9c2fd36e67de4e5d4990
Signed-off-by: Furquan Shaikh <furquan at google.com>
---
src/Kconfig | 8 --
src/cpu/intel/haswell/Kconfig | 12 ---
src/cpu/intel/haswell/Makefile.inc | 3 -
src/cpu/intel/haswell/romstage.c | 10 ---
src/cpu/intel/haswell/stage_cache.c | 26 ------
src/drivers/intel/fsp1_1/Makefile.inc | 2 -
src/drivers/intel/fsp1_1/ramstage.c | 25 +-----
src/drivers/intel/fsp1_1/romstage.c | 8 --
src/drivers/intel/fsp1_1/stage_cache.c | 28 ------
src/include/program_loading.h | 3 -
src/include/stage_cache.h | 41 ---------
src/lib/Makefile.inc | 9 --
src/lib/cbmem_stage_cache.c | 67 ---------------
src/lib/ext_stage_cache.c | 128 ----------------------------
src/lib/prog_loaders.c | 29 -------
src/soc/intel/baytrail/Kconfig | 12 ---
src/soc/intel/baytrail/Makefile.inc | 2 -
src/soc/intel/baytrail/refcode.c | 19 -----
src/soc/intel/baytrail/romstage/romstage.c | 9 --
src/soc/intel/baytrail/stage_cache.c | 31 -------
src/soc/intel/braswell/Kconfig | 13 ---
src/soc/intel/broadwell/Kconfig | 12 ---
src/soc/intel/broadwell/Makefile.inc | 2 -
src/soc/intel/broadwell/refcode.c | 19 -----
src/soc/intel/broadwell/romstage/romstage.c | 9 --
src/soc/intel/broadwell/stage_cache.c | 31 -------
src/soc/intel/skylake/Kconfig | 1 -
src/soc/intel/skylake/romstage/romstage.c | 1 -
28 files changed, 3 insertions(+), 557 deletions(-)
diff --git a/src/Kconfig b/src/Kconfig
index f9bd661..669ec00 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -246,14 +246,6 @@ config RELOCATABLE_RAMSTAGE
wake. When selecting this option the romstage is responsible for
determing a stack location to use for loading the ramstage.
-config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
- depends on RELOCATABLE_RAMSTAGE
- bool "Cache the relocated ramstage outside of cbmem."
- default n
- help
- The relocated ramstage is saved in an area specified by the
- by the board and/or chipset.
-
config FLASHMAP_OFFSET
hex "Flash Map Offset"
default 0x00670000 if NORTHBRIDGE_INTEL_SANDYBRIDGE
diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig
index ec75391..adb1050 100644
--- a/src/cpu/intel/haswell/Kconfig
+++ b/src/cpu/intel/haswell/Kconfig
@@ -47,16 +47,4 @@ config SMM_RESERVED_SIZE
hex
default 0x100000
-config RESET_ON_INVALID_RAMSTAGE_CACHE
- bool "Reset the system on S3 wake when ramstage cache invalid."
- default n
- depends on RELOCATABLE_RAMSTAGE
- help
- The haswell romstage code caches the loaded ramstage program
- in SMM space. On S3 wake the romstage will copy over a fresh
- ramstage that was cached in the SMM space. This option determines
- the action to take when the ramstage cache is invalid. If selected
- the system will reset otherwise the ramstage will be reloaded from
- cbfs.
-
endif
diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc
index d54a25c..8533ab0 100644
--- a/src/cpu/intel/haswell/Makefile.inc
+++ b/src/cpu/intel/haswell/Makefile.inc
@@ -4,12 +4,9 @@ romstage-y += romstage.c
romstage-y += tsc_freq.c
ramstage-y += acpi.c
-ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
ramstage-y += monotonic_timer.c
-romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
-
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
smm-y += monotonic_timer.c
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 9932a50..478ae2c 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -299,13 +299,3 @@ void romstage_after_car(void)
/* Load the ramstage. */
copy_and_run();
}
-
-
-#if IS_ENABLED(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM)
-void ramstage_cache_invalid(void)
-{
-#if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE
- reset_system();
-#endif
-}
-#endif
diff --git a/src/cpu/intel/haswell/stage_cache.c b/src/cpu/intel/haswell/stage_cache.c
deleted file mode 100644
index ee945c7..0000000
--- a/src/cpu/intel/haswell/stage_cache.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <cbmem.h>
-#include <stage_cache.h>
-#include "haswell.h"
-
-void stage_cache_external_region(void **base, size_t *size)
-{
- /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
- * The top of ram is defined to be the TSEG base address. */
- *size = RESERVED_SMM_SIZE;
- *base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET);
-}
diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc
index 3f214cb..f7f2106 100644
--- a/src/drivers/intel/fsp1_1/Makefile.inc
+++ b/src/drivers/intel/fsp1_1/Makefile.inc
@@ -27,14 +27,12 @@ romstage-y += raminit.c
romstage-y += romstage.c
romstage-$(CONFIG_SEPARATE_VERSTAGE) += romstage_after_verstage.S
romstage-y += stack.c
-romstage-y += stage_cache.c
ramstage-$(CONFIG_GOP_SUPPORT) += fsp_gop.c
ramstage-y += fsp_relocate.c
ramstage-y += fsp_util.c
ramstage-y += hob.c
ramstage-y += ramstage.c
-ramstage-y += stage_cache.c
ramstage-$(CONFIG_GOP_SUPPORT) += vbt.c
CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1/include
diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c
index 834f148..a00a029 100644
--- a/src/drivers/intel/fsp1_1/ramstage.c
+++ b/src/drivers/intel/fsp1_1/ramstage.c
@@ -23,7 +23,6 @@
#include <fsp/ramstage.h>
#include <fsp/util.h>
#include <lib.h>
-#include <stage_cache.h>
#include <string.h>
#include <timestamp.h>
@@ -153,19 +152,6 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup)
soc_after_silicon_init();
}
-static void fsp_cache_save(struct prog *fsp)
-{
- if (IS_ENABLED(CONFIG_DISPLAY_SMM_MEMORY_MAP))
- smm_memory_map();
-
- if (prog_entry(fsp) == NULL) {
- printk(BIOS_ERR, "ERROR: No FSP to save in cache.\n");
- return;
- }
-
- stage_cache_add(STAGE_REFCODE, fsp);
-}
-
static int fsp_find_and_relocate(struct prog *fsp)
{
if (prog_locate(fsp)) {
@@ -186,14 +172,9 @@ void intel_silicon_init(void)
struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin");
int is_s3_wakeup = acpi_is_wakeup_s3();
- if (is_s3_wakeup) {
- printk(BIOS_DEBUG, "FSP: Loading binary from cache\n");
- stage_cache_load_stage(STAGE_REFCODE, &fsp);
- } else {
- fsp_find_and_relocate(&fsp);
- printk(BIOS_DEBUG, "FSP: Saving binary in cache\n");
- fsp_cache_save(&fsp);
- }
+ fsp_find_and_relocate(&fsp);
+ if (IS_ENABLED(CONFIG_DISPLAY_SMM_MEMORY_MAP))
+ smm_memory_map();
/* FSP_INFO_HEADER is set as the program entry. */
fsp_update_fih(prog_entry(&fsp));
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index c035f60..3e69179 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -32,7 +32,6 @@
#include <romstage_handoff.h>
#include <smbios.h>
#include <soc/intel/common/mrc_cache.h>
-#include <stage_cache.h>
#include <timestamp.h>
#include <tpm.h>
#include <vendorcode/google/chromeos/chromeos.h>
@@ -386,13 +385,6 @@ __attribute__((weak)) void raminit(struct romstage_params *params)
die("ERROR - No RAM initialization specified!\n");
}
-void ramstage_cache_invalid(void)
-{
- if (IS_ENABLED(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE))
- /* Perform cold reset on invalid ramstage cache. */
- hard_reset();
-}
-
/* Display the memory configuration */
__attribute__((weak)) void report_memory_config(void)
{
diff --git a/src/drivers/intel/fsp1_1/stage_cache.c b/src/drivers/intel/fsp1_1/stage_cache.c
deleted file mode 100644
index 2d594e6..0000000
--- a/src/drivers/intel/fsp1_1/stage_cache.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2015 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <fsp/memmap.h>
-#include <stage_cache.h>
-
-void stage_cache_external_region(void **base, size_t *size)
-{
- if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) {
- printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n");
- *base = NULL;
- *size = 0;
- }
-}
diff --git a/src/include/program_loading.h b/src/include/program_loading.h
index 42addb8..aaa62393 100644
--- a/src/include/program_loading.h
+++ b/src/include/program_loading.h
@@ -167,9 +167,6 @@ void run_romstage(void);
/* Run ramstage from romstage. */
void run_ramstage(void);
-/* Called when the stage cache couldn't load ramstage on resume. */
-void ramstage_cache_invalid(void);
-
/***********************
* PAYLOAD LOADING *
***********************/
diff --git a/src/include/stage_cache.h b/src/include/stage_cache.h
deleted file mode 100644
index a24ea71..0000000
--- a/src/include/stage_cache.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _STAGE_CACHE_H_
-#define _STAGE_CACHE_H_
-
-#include <stddef.h>
-#include <stdint.h>
-#include <program_loading.h>
-
-enum {
- STAGE_RAMSTAGE,
- STAGE_REFCODE,
-};
-
-/* Cache the loaded stage provided according to the parameters. */
-void stage_cache_add(int stage_id, const struct prog *stage);
-/* Load the cached stage at given location returning the stage entry point. */
-void stage_cache_load_stage(int stage_id, struct prog *stage);
-/* Fill in parameters for the external stage cache, if utilized. */
-void stage_cache_external_region(void **base, size_t *size);
-
-/* Metadata associated with each stage. */
-struct stage_cache {
- uint64_t load_addr;
- uint64_t entry_addr;
-};
-
-#endif /* _STAGE_CACHE_H_ */
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 4c6a395..0fdc913 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -149,15 +149,6 @@ verstage-$(CONFIG_REG_SCRIPT) += reg_script.c
romstage-$(CONFIG_REG_SCRIPT) += reg_script.c
ramstage-$(CONFIG_REG_SCRIPT) += reg_script.c
-ifeq ($(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM),y)
-ramstage-y += ext_stage_cache.c
-romstage-y += ext_stage_cache.c
-else
-ramstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
-romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c
-endif
-
-
romstage-y += boot_device.c
ramstage-y += boot_device.c
diff --git a/src/lib/cbmem_stage_cache.c b/src/lib/cbmem_stage_cache.c
deleted file mode 100644
index 3fc99db..0000000
--- a/src/lib/cbmem_stage_cache.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/early_variables.h>
-#include <cbmem.h>
-#include <stage_cache.h>
-#include <string.h>
-
-/* Stage cache uses cbmem. */
-void stage_cache_add(int stage_id, const struct prog *stage)
-{
- struct stage_cache *meta;
- void *c;
-
- meta = cbmem_add(CBMEM_ID_STAGEx_META + stage_id, sizeof(*meta));
- if (meta == NULL)
- return;
- meta->load_addr = (uintptr_t)prog_start(stage);
- meta->entry_addr = (uintptr_t)prog_entry(stage);
-
- c = cbmem_add(CBMEM_ID_STAGEx_CACHE + stage_id, prog_size(stage));
- if (c == NULL)
- return;
-
- memcpy(c, prog_start(stage), prog_size(stage));
-}
-
-void stage_cache_load_stage(int stage_id, struct prog *stage)
-{
- struct stage_cache *meta;
- const struct cbmem_entry *e;
- void *c;
- size_t size;
- void *load_addr;
-
- prog_set_entry(stage, NULL, NULL);
-
- meta = cbmem_find(CBMEM_ID_STAGEx_META + stage_id);
- if (meta == NULL)
- return;
-
- e = cbmem_entry_find(CBMEM_ID_STAGEx_CACHE + stage_id);
-
- if (e == NULL)
- return;
-
- c = cbmem_entry_start(e);
- size = cbmem_entry_size(e);
- load_addr = (void *)(uintptr_t)meta->load_addr;
-
- memcpy(load_addr, c, size);
-
- prog_set_area(stage, load_addr, size);
- prog_set_entry(stage, (void *)(uintptr_t)meta->entry_addr, NULL);
-}
diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c
deleted file mode 100644
index 770097f..0000000
--- a/src/lib/ext_stage_cache.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/early_variables.h>
-#include <bootstate.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <imd.h>
-#include <rules.h>
-#include <stage_cache.h>
-#include <string.h>
-
-static struct imd imd_stage_cache CAR_GLOBAL = { };
-
-static inline struct imd *imd_get(void)
-{
- return car_get_var_ptr(&imd_stage_cache);
-}
-
-static void stage_cache_create_empty(void)
-{
- struct imd *imd;
- void *base;
- size_t size;
-
- imd = imd_get();
- stage_cache_external_region(&base, &size);
- imd_handle_init(imd, (void *)(size + (uintptr_t)base));
-
- printk(BIOS_DEBUG, "External stage cache:\n");
- imd_create_tiered_empty(imd, 4096, 4096, 1024, 32);
- if (imd_limit_size(imd, size))
- printk(BIOS_DEBUG, "Could not limit stage cache size.\n");
-}
-
-static void stage_cache_recover(void)
-{
- struct imd *imd;
- void *base;
- size_t size;
-
- imd = imd_get();
- stage_cache_external_region(&base, &size);
- imd_handle_init(imd, (void *)(size + (uintptr_t)base));
- if (imd_recover(imd))
- printk(BIOS_DEBUG, "Unable to recover external stage cache.\n");
-}
-
-void stage_cache_add(int stage_id, const struct prog *stage)
-{
- struct imd *imd;
- const struct imd_entry *e;
- struct stage_cache *meta;
- void *c;
-
- imd = imd_get();
- e = imd_entry_add(imd, CBMEM_ID_STAGEx_META + stage_id, sizeof(*meta));
-
- if (e == NULL)
- return;
-
- meta = imd_entry_at(imd, e);
-
- meta->load_addr = (uintptr_t)prog_start(stage);
- meta->entry_addr = (uintptr_t)prog_entry(stage);
-
- e = imd_entry_add(imd, CBMEM_ID_STAGEx_CACHE + stage_id,
- prog_size(stage));
-
- if (e == NULL)
- return;
-
- c = imd_entry_at(imd, e);
-
- memcpy(c, prog_start(stage), prog_size(stage));
-}
-
-void stage_cache_load_stage(int stage_id, struct prog *stage)
-{
- struct imd *imd;
- struct stage_cache *meta;
- const struct imd_entry *e;
- void *c;
- size_t size;
-
- imd = imd_get();
- e = imd_entry_find(imd, CBMEM_ID_STAGEx_META + stage_id);
- if (e == NULL)
- return;
-
- meta = imd_entry_at(imd, e);
-
- e = imd_entry_find(imd, CBMEM_ID_STAGEx_CACHE + stage_id);
-
- if (e == NULL)
- return;
-
- c = imd_entry_at(imd, e);
- size = imd_entry_size(imd, e);
-
- memcpy((void *)(uintptr_t)meta->load_addr, c, size);
-
- prog_set_area(stage, (void *)(uintptr_t)meta->load_addr, size);
- prog_set_entry(stage, (void *)(uintptr_t)meta->entry_addr, NULL);
-}
-
-static void stage_cache_setup(int is_recovery)
-{
- if (is_recovery)
- stage_cache_recover();
- else
- stage_cache_create_empty();
-}
-
-ROMSTAGE_CBMEM_INIT_HOOK(stage_cache_setup)
-RAMSTAGE_CBMEM_INIT_HOOK(stage_cache_setup)
diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c
index 14e1299..50d391b 100644
--- a/src/lib/prog_loaders.c
+++ b/src/lib/prog_loaders.c
@@ -25,7 +25,6 @@
#include <romstage_handoff.h>
#include <rmodule.h>
#include <rules.h>
-#include <stage_cache.h>
#include <symbols.h>
#include <timestamp.h>
@@ -69,27 +68,6 @@ fail:
halt();
}
-void __attribute__((weak)) stage_cache_add(int stage_id,
- const struct prog *stage) {}
-void __attribute__((weak)) stage_cache_load_stage(int stage_id,
- struct prog *stage) {}
-void __attribute__((weak)) ramstage_cache_invalid(void) {}
-
-static void run_ramstage_from_resume(struct romstage_handoff *handoff,
- struct prog *ramstage)
-{
- if (handoff != NULL && handoff->s3_resume) {
- /* Load the cached ramstage to runtime location. */
- stage_cache_load_stage(STAGE_RAMSTAGE, ramstage);
-
- if (prog_entry(ramstage) != NULL) {
- printk(BIOS_DEBUG, "Jumping to image.\n");
- prog_run(ramstage);
- }
- ramstage_cache_invalid();
- }
-}
-
static int load_relocatable_ramstage(struct prog *ramstage)
{
struct rmod_stage_load rmod_ram = {
@@ -107,11 +85,6 @@ void run_ramstage(void)
timestamp_add_now(TS_END_ROMSTAGE);
- /* Only x86 systems currently take the same firmware path on resume. */
- if (IS_ENABLED(CONFIG_ARCH_X86) && IS_ENABLED(CONFIG_EARLY_CBMEM_INIT))
- run_ramstage_from_resume(romstage_handoff_find_or_add(),
- &ramstage);
-
if (prog_locate(&ramstage))
goto fail;
@@ -123,8 +96,6 @@ void run_ramstage(void)
} else if (cbfs_prog_stage_load(&ramstage))
goto fail;
- stage_cache_add(STAGE_RAMSTAGE, &ramstage);
-
timestamp_add_now(TS_END_COPYRAM);
prog_run(&ramstage);
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index fcf382e..69298ca 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -134,18 +134,6 @@ config DCACHE_RAM_ROMSTAGE_STACK_SIZE
The amount of anticipated stack usage from the data cache
during pre-RAM ROM stage execution.
-config RESET_ON_INVALID_RAMSTAGE_CACHE
- bool "Reset the system on S3 wake when ramstage cache invalid."
- default n
- depends on RELOCATABLE_RAMSTAGE
- help
- The baytrail romstage code caches the loaded ramstage program
- in SMM space. On S3 wake the romstage will copy over a fresh
- ramstage that was cached in the SMM space. This option determines
- the action to take when the ramstage cache is invalid. If selected
- the system will reset otherwise the ramstage will be reloaded from
- cbfs.
-
config ENABLE_BUILTIN_COM1
bool "Enable builtin COM1 Serial Port"
default n
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index edc77af..f2ecca6 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -44,8 +44,6 @@ ramstage-y += pcie.c
ramstage-y += sd.c
ramstage-y += dptf.c
ramstage-y += perf_power.c
-ramstage-y += stage_cache.c
-romstage-y += stage_cache.c
ramstage-$(CONFIG_ELOG) += elog.c
ramstage-y += hda.c
diff --git a/src/soc/intel/baytrail/refcode.c b/src/soc/intel/baytrail/refcode.c
index a5946bc..5af4b9c 100644
--- a/src/soc/intel/baytrail/refcode.c
+++ b/src/soc/intel/baytrail/refcode.c
@@ -21,7 +21,6 @@
#include <cpu/x86/tsc.h>
#include <program_loading.h>
#include <rmodule.h>
-#include <stage_cache.h>
#include <soc/ramstage.h>
#include <soc/efi_wrapper.h>
@@ -31,17 +30,6 @@ static void ABI_X86 send_to_console(unsigned char b)
console_tx_byte(b);
}
-static efi_wrapper_entry_t load_refcode_from_cache(void)
-{
- struct prog refcode;
-
- printk(BIOS_DEBUG, "refcode loading from cache.\n");
-
- stage_cache_load_stage(STAGE_REFCODE, &refcode);
-
- return (efi_wrapper_entry_t)prog_entry(&refcode);
-}
-
static efi_wrapper_entry_t load_reference_code(void)
{
struct prog prog =
@@ -51,10 +39,6 @@ static efi_wrapper_entry_t load_reference_code(void)
.prog = &prog,
};
- if (acpi_is_wakeup_s3()) {
- return load_refcode_from_cache();
- }
-
if (prog_locate(&prog)) {
printk(BIOS_DEBUG, "Couldn't locate reference code.\n");
return NULL;
@@ -65,9 +49,6 @@ static efi_wrapper_entry_t load_reference_code(void)
return NULL;
}
- /* Cache loaded reference code. */
- stage_cache_add(STAGE_REFCODE, &prog);
-
return prog_entry(&prog);
}
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 3668235..3d65886 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -27,7 +27,6 @@
#endif
#include <elog.h>
#include <romstage_handoff.h>
-#include <stage_cache.h>
#include <timestamp.h>
#include <tpm.h>
#include <vendorcode/google/chromeos/chromeos.h>
@@ -348,14 +347,6 @@ static void *setup_stack_and_mttrs(void)
return slot;
}
-void ramstage_cache_invalid(void)
-{
-#if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE
- /* Perform cold reset on invalid ramstage cache. */
- cold_reset();
-#endif
-}
-
int get_sw_write_protect_state(void)
{
u8 status;
diff --git a/src/soc/intel/baytrail/stage_cache.c b/src/soc/intel/baytrail/stage_cache.c
deleted file mode 100644
index 4c2a976..0000000
--- a/src/soc/intel/baytrail/stage_cache.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <cbmem.h>
-#include <stage_cache.h>
-#include <soc/smm.h>
-
-void stage_cache_external_region(void **base, size_t *size)
-{
- char *smm_base;
- /* 1MiB cache size */
- const long cache_size = CONFIG_SMM_RESERVED_SIZE;
-
- /* Ramstage cache lives in TSEG region which is the definition of
- * cbmem_top(). */
- smm_base = cbmem_top();
- *size = cache_size;
- *base = &smm_base[smm_region_size() - cache_size];
-}
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index 3c6f788..24d3729 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -12,7 +12,6 @@ config CPU_SPECIFIC_OPTIONS
select ARCH_ROMSTAGE_X86_32
select ARCH_VERSTAGE_X86_32
select CACHE_MRC_SETTINGS
- select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE
select COLLECT_TIMESTAMPS
select SUPPORT_CPU_UCODE_IN_CBFS
select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
@@ -100,18 +99,6 @@ config DCACHE_RAM_ROMSTAGE_STACK_SIZE
The amount of anticipated stack usage from the data cache
during pre-ram rom stage execution.
-config RESET_ON_INVALID_RAMSTAGE_CACHE
- bool "Reset the system on S3 wake when ramstage cache invalid."
- default n
- depends on RELOCATABLE_RAMSTAGE
- help
- The haswell romstage code caches the loaded ramstage program
- in SMM space. On S3 wake the romstage will copy over a fresh
- ramstage that was cached in the SMM space. This option determines
- the action to take when the ramstage cache is invalid. If selected
- the system will reset otherwise the ramstage will be reloaded from
- cbfs.
-
config ENABLE_BUILTIN_COM1
bool "Enable builtin COM1 Serial Port"
default n
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 1c29d77..59a21b2 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -13,7 +13,6 @@ config CPU_SPECIFIC_OPTIONS
select ARCH_RAMSTAGE_X86_32
select CACHE_MRC_SETTINGS
select MRC_SETTINGS_PROTECT
- select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select SUPPORT_CPU_UCODE_IN_CBFS
select HAVE_MONOTONIC_TIMER
@@ -146,17 +145,6 @@ config PRE_GRAPHICS_DELAY
VBIOS. On those systems we need to wait for a bit before executing
the VBIOS.
-config RESET_ON_INVALID_RAMSTAGE_CACHE
- bool "Reset the system on S3 wake when ramstage cache invalid."
- default n
- depends on RELOCATABLE_RAMSTAGE
- help
- The romstage code caches the loaded ramstage program in SMM space.
- On S3 wake the romstage will copy over a fresh ramstage that was
- cached in the SMM space. This option determines the action to take
- when the ramstage cache is invalid. If selected the system will
- reset otherwise the ramstage will be reloaded from cbfs.
-
config INTEL_PCH_UART_CONSOLE
bool "Use Serial IO UART for console"
default n
diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc
index 4da8c20..eafaeb9 100644
--- a/src/soc/intel/broadwell/Makefile.inc
+++ b/src/soc/intel/broadwell/Makefile.inc
@@ -54,8 +54,6 @@ smm-y += smihandler.c
ramstage-y += smmrelocate.c
ramstage-y += spi.c
smm-$(CONFIG_SPI_FLASH_SMM) += spi.c
-ramstage-y += stage_cache.c
-romstage-y += stage_cache.c
ramstage-y += systemagent.c
ramstage-y += tsc_freq.c
romstage-y += tsc_freq.c
diff --git a/src/soc/intel/broadwell/refcode.c b/src/soc/intel/broadwell/refcode.c
index c818752..23f4ed1 100644
--- a/src/soc/intel/broadwell/refcode.c
+++ b/src/soc/intel/broadwell/refcode.c
@@ -21,24 +21,12 @@
#include <cpu/x86/tsc.h>
#include <program_loading.h>
#include <rmodule.h>
-#include <stage_cache.h>
#include <string.h>
#include <soc/pei_data.h>
#include <soc/pei_wrapper.h>
#include <soc/pm.h>
#include <soc/ramstage.h>
-static pei_wrapper_entry_t load_refcode_from_cache(void)
-{
- struct prog refcode;
-
- printk(BIOS_DEBUG, "refcode loading from cache.\n");
-
- stage_cache_load_stage(STAGE_REFCODE, &refcode);
-
- return (pei_wrapper_entry_t)prog_entry(&refcode);
-}
-
static pei_wrapper_entry_t load_reference_code(void)
{
struct prog prog =
@@ -48,10 +36,6 @@ static pei_wrapper_entry_t load_reference_code(void)
.prog = &prog,
};
- if (acpi_is_wakeup_s3()) {
- return load_refcode_from_cache();
- }
-
if (prog_locate(&prog)) {
printk(BIOS_DEBUG, "Couldn't locate reference code.\n");
return NULL;
@@ -62,9 +46,6 @@ static pei_wrapper_entry_t load_reference_code(void)
return NULL;
}
- /* Cache loaded reference code. */
- stage_cache_add(STAGE_REFCODE, &prog);
-
return (pei_wrapper_entry_t)prog_entry(&prog);
}
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index 762758d..4bfe796 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -27,7 +27,6 @@
#include <elog.h>
#include <tpm.h>
#include <romstage_handoff.h>
-#include <stage_cache.h>
#include <timestamp.h>
#include <soc/me.h>
#include <soc/pei_data.h>
@@ -133,14 +132,6 @@ void asmlinkage romstage_after_car(void)
while (1);
}
-void ramstage_cache_invalid(void)
-{
-#if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE
- /* Perform cold reset on invalid ramstage cache. */
- reset_system();
-#endif
-}
-
int get_sw_write_protect_state(void)
{
u8 status;
diff --git a/src/soc/intel/broadwell/stage_cache.c b/src/soc/intel/broadwell/stage_cache.c
deleted file mode 100644
index 03c6357..0000000
--- a/src/soc/intel/broadwell/stage_cache.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <cbmem.h>
-#include <soc/smm.h>
-#include <stage_cache.h>
-#include <stdint.h>
-
-void stage_cache_external_region(void **base, size_t *size)
-{
- /* The ramstage cache lives in the TSEG region.
- * The top of ram is defined to be the TSEG base address. */
- u32 offset = smm_region_size();
- offset -= CONFIG_IED_REGION_SIZE;
- offset -= CONFIG_SMM_RESERVED_SIZE;
-
- *base = (void *)(cbmem_top() + offset);
- *size = CONFIG_SMM_RESERVED_SIZE;
-}
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 0b7dc8c..32e4379 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -13,7 +13,6 @@ config CPU_SPECIFIC_OPTIONS
select ARCH_VERSTAGE_X86_32
select ACPI_NHLT
select CACHE_MRC_SETTINGS
- select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE
select COLLECT_TIMESTAMPS
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select GENERIC_GPIO_LIB
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 9c61095..4dfe7a6 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -38,7 +38,6 @@
#include <soc/serialio.h>
#include <soc/romstage.h>
#include <soc/spi.h>
-#include <stage_cache.h>
#include <timestamp.h>
#include <vendorcode/google/chromeos/chromeos.h>
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