[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/apollolake: Correct PCI write size in romstage

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit c681409a8a3429c8aa8572ce18f4560fecb0c0ae
Author: Furquan Shaikh <furquan at google.com>
Date:   Wed May 4 16:03:36 2016 -0700

    soc/intel/apollolake: Correct PCI write size in romstage
    
    1. PCI command reg write should be 16-bit.
    2. HPTC reg write should be 8-bit. Also, use macros instead of
    hard-coded values. Currently, the macros are defined in romstage.c,
    but if more P2SB macros are added, it would be good to move them to a
    separate header file.
    
    Change-Id: Iad1eb6a95467a41ecf454092808d357425c4c2fc
    Signed-off-by: Furquan Shaikh <furquan at google.com>
    Reviewed-on: https://review.coreboot.org/14613
    Tested-by: build bot (Jenkins)
    Reviewed-by: Andrey Petrov <andrey.petrov at intel.com>


See https://review.coreboot.org/14613 for details.

-gerrit