[coreboot-gerrit] Patch set updated for coreboot: intel/amenia: Declare ChromeEC in devicetree.cb
Alexandru Gagniuc (alexandrux.gagniuc@intel.com)
gerrit at coreboot.org
Tue May 3 20:35:07 CEST 2016
Alexandru Gagniuc (alexandrux.gagniuc at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14591
-gerrit
commit 1a4a131a4aeab3ce6c23a175ffe9839063a94827
Author: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
Date: Tue May 3 11:25:03 2016 -0700
intel/amenia: Declare ChromeEC in devicetree.cb
This allows the chomeec driver to declare its resources so that IO
windows to LPC are opened up during resource allocation.
Change-Id: Ife98ecb4cbf5393493e6c71742de8d37953df548
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
---
src/mainboard/intel/amenia/devicetree.cb | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb
index c54e838..38a2de2 100644
--- a/src/mainboard/intel/amenia/devicetree.cb
+++ b/src/mainboard/intel/amenia/devicetree.cb
@@ -46,7 +46,11 @@ chip soc/intel/apollolake
device pci 1b.0 on end # - SDCARD
device pci 1c.0 on end # - eMMC
device pci 1e.0 on end # - SDIO
- device pci 1f.0 on end # - LPC
+ device pci 1f.0 on # - LPC
+ chip ec/google/chromeec
+ device pnp 0c09.0 on end
+ end
+ end
device pci 1f.1 on end # - SMBUS
end
end
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